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Author SHA1 Message Date
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00
Alex Forencich
8214e2abf9 added axis as a subproject 
git-subtree-dir: lib/axis
git-subtree-mainline: d64445b9e057cf97ae8fd57fbe83c5505c6ba45c
git-subtree-split: ac2f7e546df3b7f4a936cdb4d558adc517c5ddb4
 2014-11-05 17:25:00 -08:00
Alex Forencich
d64445b9e0 Add git subdir script for axis lib 2014-11-05 17:24:48 -08:00
Alex Forencich
96c6fcd144 Remove AXI stream components 2014-11-05 16:59:59 -08:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
849f3c174a Add .travis.yml 2014-11-05 16:22:09 -08:00
Alex Forencich
0507fd4ca9 Update readme 2014-11-05 16:19:00 -08:00
Alex Forencich
588c2742e8 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
af0dce33b1 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
0f62d31fef Rework ARP datapath modules to separate output register 2014-10-28 01:55:36 -07:00
Alex Forencich
4474181549 Rework UDP datapath modules to separate output register 2014-10-28 01:55:29 -07:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
f827b5eafb Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
0b8a36d5e7 Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
d82ebcce17 Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
a2a509884e Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
c86ffa1202 Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
47a8c35d5d Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
a9bbdae908 Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
a92eb4e57f Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
2cf95840ee Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
7e01c6c14c Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
3b1655f81f Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
63843e9d5d Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
09d0d87939 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
8e9b38cde0 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
8bce338bc0 Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
2495dd2bac Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
2ec83046f6 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
f53f4aa504 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
ca50423036 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
6ab2a86e13 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00
Alex Forencich
e14a79dee4 Add IP module and testbench 2014-09-29 22:26:55 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00
Alex Forencich
20da100db6 Add UDP transmit and receive modules 2014-09-25 16:52:42 -07:00
Alex Forencich
0f1eb94148 Calculate header checksum for truncated packets 2014-09-25 16:26:59 -07:00
Alex Forencich
ebc1c7ccc6 Rename checksum to calc_checksum in ip_ep 2014-09-25 16:26:23 -07:00
Alex Forencich
8191b38e7a Move header valid assign to top 2014-09-25 16:25:37 -07:00
Alex Forencich
c6236bc647 Add 64-bit datapath version of IP modules 2014-09-25 00:40:48 -07:00
Alex Forencich
3bee612dfd Add extra delays to IP testbenches 2014-09-25 00:39:22 -07:00