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Author	SHA1	Message	Date
Alex Forencich	09759518fc	ID always zero if ID pins not connected	2018-08-14 21:48:24 -07:00
Alex Forencich	649179894a	Remove unnecessary asserts	2018-08-14 21:46:05 -07:00
Alex Forencich	2113bb1795	Add AXI registers and testbenches	2018-08-13 23:36:47 -07:00
Alex Forencich	5f302d8106	Fix some more issues in AXI RAM module	2018-08-13 16:00:29 -07:00
Alex Forencich	66b20c171b	Add AXI FIFOs and testbenches	2018-08-13 15:31:04 -07:00
Alex Forencich	a962dfce72	Properly handle read bursts in AXI model	2018-08-13 15:12:56 -07:00
Alex Forencich	7e18825ba2	Fix 4k align	2018-08-12 23:08:38 -07:00
Alex Forencich	aed7cf9d9b	Print burst debugging information	2018-08-12 22:37:28 -07:00
Alex Forencich	ed27cebed8	Add max_burst_len parameter	2018-08-11 23:09:28 -07:00
Alex Forencich	e29114fe04	Check for disconnected ports	2018-08-11 23:09:00 -07:00
Alex Forencich	0cb456e047	Improve testbench and fix bugs in axi_ram	2018-08-11 22:32:05 -07:00
Alex Forencich	4ee04f6682	Support pausing channels in AXI models	2018-08-11 21:47:08 -07:00
Alex Forencich	14d8819cd3	merged changes in axis	2018-08-09 18:41:34 -07:00
Alex Forencich	8e5ec36ced	Optimize axis_arb_mux and improve latency	2018-08-09 18:40:50 -07:00
Alex Forencich	7a879aec1c	Remove extra registers	2018-08-09 18:38:41 -07:00
Alex Forencich	b5ec1c4a30	merged changes in axis	2018-08-09 11:24:21 -07:00
Alex Forencich	202fbcbb6f	Fix typo	2018-08-09 11:23:27 -07:00
Alex Forencich	048c0bb5e5	Updates for python 2	2018-08-06 15:02:59 -07:00
Alex Forencich	947e700dc2	Support omitting id signals	2018-08-02 17:27:40 -07:00
Alex Forencich	e78f865ddf	Fix 4K boundary assert	2018-07-30 17:54:23 -07:00
Alex Forencich	f4cca52660	Initial commit	2018-07-29 19:04:30 -07:00
Alex Forencich	2e9602b5b4	Update testbenches to use wait	2018-07-02 18:20:07 -07:00
Alex Forencich	65c64588a6	More endpoint updates	2018-07-02 16:33:13 -07:00
Alex Forencich	7775e7774d	merged changes in axis	2018-07-02 16:26:21 -07:00
Alex Forencich	ffc63e4b0d	Update readme	2018-07-02 16:25:29 -07:00
Alex Forencich	3063bba54b	Update testbenches to use wait	2018-07-02 16:19:35 -07:00
Alex Forencich	9390c3639b	More endpoint updates	2018-07-02 14:13:47 -07:00
Alex Forencich	63f9bbeced	Update endpoints	2018-07-02 13:20:49 -07:00
Alex Forencich	4cb51ac84e	merged changes in axis	2018-07-02 10:25:51 -07:00
Alex Forencich	268d011b89	Add wait method to sink	2018-06-30 00:21:26 -07:00
Alex Forencich	2ebffeb223	Be more pythonic	2018-06-30 00:21:02 -07:00
Alex Forencich	8982b4f4e1	Fix modsell pin	2018-06-29 13:00:41 -07:00
Alex Forencich	cd51821bf7	Add parameters	2018-06-22 18:56:05 -07:00
Alex Forencich	5b7646ccda	Rework ARP subsystem	2018-06-18 13:59:58 -07:00
Alex Forencich	25d1b373cc	Use don't care bits	2018-06-14 15:20:20 -07:00
Alex Forencich	6368529b6f	Add clock frequency annotation	2018-06-14 13:42:10 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	20486d438a	merged changes in axis	2018-06-13 22:36:26 -07:00
Alex Forencich	c5837daa2f	Update testbenches to use instances()	2018-06-13 22:26:10 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	8e1f14e9a7	Add VCU118 10G example design	2018-06-13 19:30:07 -07:00
Alex Forencich	05c6743473	Update xdc	2018-06-13 19:18:59 -07:00
Alex Forencich	f4d7edf23f	Add VCU118 example design	2018-06-13 14:33:07 -07:00
Alex Forencich	415f723edc	Fix clock name	2018-06-11 16:37:34 -07:00
Alex Forencich	fea477db09	Add unused ports	2018-06-11 16:36:44 -07:00
Alex Forencich	3ae97c71a0	Add documentation	2018-06-04 18:21:55 -07:00
Alex Forencich	e95b39b36d	Update iddr/oddr Altera device support	2018-06-04 18:20:31 -07:00
Alex Forencich	c31757552b	Add crosspoint design	2018-05-31 16:27:56 -07:00
Alex Forencich	855b593ce5	Minor updates to 10G example designs	2018-05-31 16:05:41 -07:00
Alex Forencich	3e28af152a	Fix CI	2018-02-27 11:00:31 -08:00