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Author SHA1 Message Date
Alex Forencich
f93310b85b Add GMIIFrame object and add tests and asserts for GMII error signal 2015-05-07 19:10:44 -07:00
Alex Forencich
3a180bd24f Improve error signal handling 2015-05-07 19:08:16 -07:00
Alex Forencich
0be84e3b03 Write to _next instead of _reg in async block 2015-05-04 01:17:39 -07:00
Alex Forencich
1e05fab4ee merged changes in axis 2015-05-03 00:25:29 -07:00
Alex Forencich
14f2d5e9f7 Add tkeep asserts to AXI stream EP 2015-05-03 00:23:58 -07:00
Alex Forencich
71511b3671 Remove unused register 2015-04-20 23:37:57 -07:00
Alex Forencich
4a46cf72fd merged changes in axis 2015-04-19 23:34:04 -07:00
Alex Forencich
9cca78bc7c Fix last cycle detect logic 2015-04-19 23:33:34 -07:00
Alex Forencich
7795a9182b Remove tristate for state machine inference 2015-04-19 23:08:41 -07:00
Alex Forencich
966e47a826 Fix RAM and register widths 2015-04-19 23:06:30 -07:00
Alex Forencich
b4030d61ce merged changes in axis 2015-04-19 17:52:16 -07:00
Alex Forencich
9b7bad92f2 Reset pointers correctly 2015-04-19 17:51:27 -07:00
Alex Forencich
5341987c45 Manage ethernet preamble properly 2015-04-01 19:44:25 -07:00
Alex Forencich
92830f87d8 Update for Python 3 2015-04-01 19:43:54 -07:00
Alex Forencich
db6a6e23f5 Add 64 bit Ethernet FCS checker 2015-03-22 01:05:57 -07:00
Alex Forencich
ae7758d835 Add .travis.yml 2015-03-21 22:31:22 -07:00
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
101d963c09 Update AXI stream endpoint 2015-03-21 21:44:16 -07:00
Alex Forencich
ea5809be5e merged changes in axis 2015-03-21 04:58:56 -07:00
Alex Forencich
8cd0d3ee06 Update .travis.yml 2015-03-21 04:49:43 -07:00
Alex Forencich
eb9f7c13f1 Update .travis.yml 2015-03-21 04:47:21 -07:00
Alex Forencich
684f6967e5 Update .travis.yml 2015-03-21 04:40:57 -07:00
Alex Forencich
646ad2a293 Update .travis.yml 2015-03-21 04:39:27 -07:00
Alex Forencich
6bd28aa128 Update .travis.yml 2015-03-21 04:36:54 -07:00
Alex Forencich
d9c41d43f0 Update .travis.yml 2015-03-21 04:28:53 -07:00
Alex Forencich
d00471352f Update .travis.yml 2015-03-21 04:24:52 -07:00
Alex Forencich
7b991bfe0e Update AXI stream endpoint to support multiple tdata signals 2015-03-21 03:35:42 -07:00
Alex Forencich
30e597e3e0 Test with python 3 2015-03-21 03:32:42 -07:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
54bfdaa8c0 Cast WL to int 2015-03-21 03:19:43 -07:00
Alex Forencich
4981d7cacd Update MyHDL repo 2015-03-21 02:56:17 -07:00
Alex Forencich
3138795899 Fix rate limiter testbenches 2015-03-21 02:55:30 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
d73b296903 Properly handle short packets 2015-03-04 13:06:29 -08:00
Alex Forencich
8ba6cf00d6 Test very short packets 2015-03-04 12:58:22 -08:00
Alex Forencich
17ad08e412 Add 64-bit Ethernet FCS inserter 2015-03-04 00:33:26 -08:00
Alex Forencich
263891b3f6 Make sure all paths set state_next 2015-03-04 00:31:41 -08:00
Alex Forencich
47a3a50b65 Move preamble out of gmii endpoint 2015-03-03 23:47:27 -08:00
Alex Forencich
23fa1f1207 Handle tlast on first cycle 2015-03-03 21:46:02 -08:00
Alex Forencich
43999fb360 Add testbench for FCS insert with padding 2015-03-03 00:46:53 -08:00
Alex Forencich
ff14639eea Test FCS inserter with padding insertion enabled 2015-02-28 23:13:02 -08:00
Alex Forencich
d3e30d0a73 Fix padding bug 2015-02-28 23:09:41 -08:00
Alex Forencich
08dd43defc Add frame length asserts to gigabit MAC testbench 2015-02-28 23:08:53 -08:00
Alex Forencich
d489468776 Add example design for Digilent Atlys board 2015-02-28 20:05:05 -08:00
Alex Forencich
5a5c78be64 merged changes in axis 2015-02-28 19:32:38 -08:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
14e71d568d Improve classifier logic by registering payload select signals 2015-02-28 19:14:22 -08:00
Alex Forencich
d57c857d88 Put PHY interface registers into IOBs for timing 2015-02-28 18:24:20 -08:00
Alex Forencich
7532915bb7 Add GMII PHY interface module 2015-02-28 01:11:03 -08:00
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00