FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
132 Commits 1 Branch 0 Tags
Commit Graph

65 Commits

Author SHA1 Message Date
Alex Forencich
9bf6f01649 Add 2 port Ethernet mux components 2014-11-21 00:02:20 -08:00
Alex Forencich
96b6e7ca96 Ignore transient requests 2014-11-21 00:00:27 -08:00
Alex Forencich
d483ebb8da Drop arp request earlier 2014-11-20 23:59:54 -08:00
Alex Forencich
2ae3581144 Add ARP module and testbench 2014-11-20 22:55:28 -08:00
Alex Forencich
7fdb7b4f35 Add ARP cache module 2014-11-20 22:54:08 -08:00
Alex Forencich
f35ecece83 Initialize tkeep properly 2014-11-20 22:52:52 -08:00
Alex Forencich
fc6ccd97fb Rework IP modules 2014-11-20 12:11:11 -08:00
Alex Forencich
64f6488bf1 Add UDP demux module and testbench 2014-11-18 15:17:50 -08:00
Alex Forencich
1b69fc5eed Add UDP arbitrated mux and testbench 2014-11-18 14:53:31 -08:00
Alex Forencich
a5d68fcff9 Add UDP mux module and testbench 2014-11-18 14:41:48 -08:00
Alex Forencich
348a347616 Add IP demux and testbench 2014-11-18 12:36:12 -08:00
Alex Forencich
fbca60e65e Add IP arbitrated mux and testbench 2014-11-18 11:48:11 -08:00
Alex Forencich
f6fcec08f3 Add IP mux module and testbench 2014-11-18 11:27:34 -08:00
Alex Forencich
4db581ae3c Add ethernet demux module and testbench 2014-11-17 21:52:49 -08:00
Alex Forencich
885d847514 Rework header ready set 2014-11-17 19:27:45 -08:00
Alex Forencich
59952bd8cf Do not accept new frame until header is read 2014-11-17 18:10:35 -08:00
Alex Forencich
4d1180d74c Reverse priority in arbitrated mux 2014-11-16 02:20:44 -08:00
Alex Forencich
f1d075d974 Add enable signal 2014-11-16 02:13:43 -08:00
Alex Forencich
c90d5141ac Add ethernet arbitrated mux module and testbench 2014-11-14 22:11:49 -08:00
Alex Forencich
9bee01e74c Add ethernet mux and testbench 2014-11-14 17:48:51 -08:00
Alex Forencich
96c6fcd144 Remove AXI stream components 2014-11-05 16:59:59 -08:00
Alex Forencich
588c2742e8 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
0f62d31fef Rework ARP datapath modules to separate output register 2014-10-28 01:55:36 -07:00
Alex Forencich
4474181549 Rework UDP datapath modules to separate output register 2014-10-28 01:55:29 -07:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
0b8a36d5e7 Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
d82ebcce17 Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
c86ffa1202 Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
a9bbdae908 Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
2cf95840ee Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
7e01c6c14c Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
09d0d87939 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
8e9b38cde0 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
8bce338bc0 Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
2495dd2bac Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
f53f4aa504 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
6ab2a86e13 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00
Alex Forencich
e14a79dee4 Add IP module and testbench 2014-09-29 22:26:55 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00
Alex Forencich
20da100db6 Add UDP transmit and receive modules 2014-09-25 16:52:42 -07:00
Alex Forencich
8191b38e7a Move header valid assign to top 2014-09-25 16:25:37 -07:00
Alex Forencich
c6236bc647 Add 64-bit datapath version of IP modules 2014-09-25 00:40:48 -07:00
Alex Forencich
d052bbb2bf Update 64-bit ethernet modules with lane shifting logic 2014-09-25 00:38:36 -07:00
Alex Forencich
ac57a22050 Abort with early termination error on last assert on first header word 2014-09-25 00:37:14 -07:00
Alex Forencich
5eaba1c3b3 Do not clock out a header if the last signal falls on the last word 2014-09-24 23:52:41 -07:00
Alex Forencich
c9a2b89717 Remove unused register 2014-09-24 01:12:48 -07:00
Alex Forencich
c74d2d1127 Update comment 2014-09-21 15:55:02 -07:00