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274 Commits 1 Branch 0 Tags
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15 Commits

Author SHA1 Message Date
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
60a2813fbc Fix indentation 2019-12-05 22:09:04 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
ee532a2472 Check tag count based on target device 2019-11-15 14:57:23 -08:00
Alex Forencich
52c502227f Remove unused client tag ports and parameters 2019-11-15 00:55:13 -08:00
Alex Forencich
553d7e05fe Update AXI DMA modules to support 512 bit interface 2019-10-14 16:22:09 -07:00
Alex Forencich
e7630ef350 Expose parameter in wrapper 2019-10-02 23:21:49 -07:00
Alex Forencich
e97e4ad423 Parametrize tuser signal widths 2019-09-26 23:30:03 -07:00
Alex Forencich
e3ad96ef07 Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux 2019-09-17 16:32:47 -07:00
Alex Forencich
c75f29c648 Add parameter documentation 2019-07-24 18:01:13 -07:00
Alex Forencich
5d42112477 Enable PCIe extended tag based on tag count 2019-03-21 00:01:48 -07:00
Alex Forencich
b592c7d7af Add missing parameter 2019-03-03 22:32:35 -08:00
Alex Forencich
56ebc966e1 Update parameters 2019-03-03 13:37:34 -08:00
Alex Forencich
28fa143ae5 Add Ultrascale PCIe DMA modules and testbenches 2018-11-26 23:23:54 -08:00