7 Commits

Author	SHA1	Message	Date
Alex Forencich	cc5fead04d	Convert to synchronous resets	2015-10-09 22:36:58 -07:00
Alex Forencich	51b5335318	Remove z from default states for FSM inference	2015-03-09 02:38:39 -07:00
Alex Forencich	0e26b3a8a4	Put back lane shifting logic	2014-10-28 00:54:15 -07:00
Alex Forencich	205be7ed27	Rework AXI ethernet modules to separate output register	2014-10-23 00:05:06 -07:00
Alex Forencich	ac57a22050	Abort with early termination error on last assert on first header word	2014-09-25 00:37:14 -07:00
Alex Forencich	85d11645eb	Rename frame_error to error_header_early_termination	2014-09-15 19:08:01 -07:00
Alex Forencich	8e4d162667	Add ethernet frame to AXI stream modules	2014-09-14 01:06:48 -07:00