88 Commits

Author	SHA1	Message	Date
Alex Forencich	a196cd227c	Enable bus mastering and MSI in driver model	2020-03-12 15:32:08 -07:00
Alex Forencich	457f4d7f3f	Use configured ring stride	2020-03-12 15:28:00 -07:00
Alex Forencich	0c32192226	Use constants instead of magic numbers	2020-03-12 15:08:20 -07:00
Alex Forencich	1216f7a76e	Offset packet start by 10 bytes to match Linux kernel skb alignment	2020-03-08 21:56:08 -07:00
Alex Forencich	23aef37aff	Rewrite resets	2020-03-08 16:56:06 -07:00
Alex Forencich	248a0b4f93	Convert descriptor to DMA operation without storing in table	2020-03-08 00:22:55 -08:00
Alex Forencich	f7a1a7ef95	Add descriptor FIFOs	2020-03-07 22:28:59 -08:00
Alex Forencich	4dd5104f4d	Stripe completion queues across event queues	2020-03-06 00:58:30 -08:00
Alex Forencich	627153cd9b	Fix signal sizing bug	2020-03-06 00:24:13 -08:00
Alex Forencich	2b14ab2555	Update cmac_pad to pad frames to 60 bytes	2020-02-26 13:36:19 -08:00
Alex Forencich	217217b45e	Remove unused table fields	2019-12-30 22:02:22 -08:00
Alex Forencich	f642bb7f7e	Reserve packet data slot early and release on dequeue fail	2019-12-30 17:49:42 -08:00
Alex Forencich	3690fdeb7d	Pull out pipeline parameters	2019-12-28 01:16:16 -08:00
Alex Forencich	58200e9851	Fix testbench	2019-12-28 01:15:40 -08:00
Alex Forencich	db9e1df1fa	Update pipelining to enable URAM inference	2019-12-28 01:13:57 -08:00
Alex Forencich	f97ff4407b	Change driver model max packet size	2019-12-23 14:41:52 -08:00
Alex Forencich	cbde1abaf9	Add CMAC pad module	2019-12-23 14:40:51 -08:00
Alex Forencich	45a33b8293	Fix scheduler bug	2019-12-16 14:13:01 -08:00
Alex Forencich	7a68abbb84	Split control and data descriptor paths to DMA engine	2019-12-13 14:15:25 -08:00
Alex Forencich	4dafedca27	Reschedule queue if necessary	2019-12-06 14:21:20 -08:00
Alex Forencich	6270278c75	Add RSS support	2019-12-06 14:15:16 -08:00
Alex Forencich	b5d7bd15b4	Add rx_hash module and testbenches	2019-12-05 13:47:07 -08:00
Alex Forencich	317aa34db5	Expose control bits	2019-11-21 15:12:49 -08:00
Alex Forencich	463f2053b0	Add port register port_mtu	2019-11-18 16:30:32 -08:00
Alex Forencich	03465b4b25	Fix parameter	2019-11-18 16:27:02 -08:00
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	bce2756c0c	Parametrize checksum offload	2019-11-13 23:49:50 -08:00
Alex Forencich	c954b55da9	Remove tx_scheduler_tdma_rr module	2019-11-05 22:10:47 -08:00
Alex Forencich	3655a6df00	Use new TDMA scheduler control module	2019-11-05 22:09:51 -08:00
Alex Forencich	7fb022abe1	Add tx_scheduler_ctrl_tdma module	2019-11-05 18:24:22 -08:00
Alex Forencich	f53a6b20e8	Add timeslot count to port registers	2019-11-05 16:59:40 -08:00
Alex Forencich	f65b139797	Add scheduler control input to tx_scheduler_rr	2019-11-05 16:56:10 -08:00
Alex Forencich	304e0b7410	Update TDMA scheduler to generate status signals and avoid producing runt outputs	2019-11-05 16:55:19 -08:00
Alex Forencich	e92485a41e	Fix register definitions	2019-11-05 16:44:57 -08:00
Alex Forencich	381fd871c5	Parametrize tag widths	2019-10-31 23:25:34 -07:00
Alex Forencich	736321641f	Parametrize addressing	2019-10-31 23:24:42 -07:00
Alex Forencich	415c2b36be	Remove old code	2019-10-19 00:38:52 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	89b7eccb38	Missed some changes	2019-09-26 23:51:18 -07:00
Alex Forencich	c6e75b40a1	Don't need AXI DMA unaligned support	2019-09-23 18:11:25 -07:00
Alex Forencich	2325966973	Pull out descriptor and completion handling logic	2019-09-23 18:10:35 -07:00
Alex Forencich	6aa48f9127	Add completion op mux module	2019-09-23 14:47:09 -07:00
Alex Forencich	9219957013	Add descriptor op mux module	2019-09-23 14:47:00 -07:00
Alex Forencich	009a80aff2	Add completion write module	2019-09-23 14:44:08 -07:00
Alex Forencich	75a756e915	Add descriptor fetch module	2019-09-23 14:41:35 -07:00
Alex Forencich	2e27d6ae2f	Improve tx_scheduler_rr timing	2019-09-14 23:32:34 -07:00
Alex Forencich	bee056e7d3	Fix pipelining bug	2019-09-13 13:48:48 -07:00
Alex Forencich	132d44cd90	Increase crossbar threads count	2019-09-11 18:06:14 -07:00
Alex Forencich	5048864d86	Update tx_scheduler to handle out of order operations	2019-09-02 09:02:53 -07:00
Alex Forencich	e0a1e49d7b	Update tx_engine to return status early in case of dequeue fail	2019-09-02 08:17:09 -07:00