40 Commits

Author	SHA1	Message	Date
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	151ed7e179	Add extra reset registers	2021-01-31 11:10:03 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	53f4275ea2	Add output registers for I2C interface to improve timing	2020-10-13 23:52:52 -07:00
Alex Forencich	d6810db7f5	Add extra output register for flash interface to improve routability and timing	2020-10-08 19:22:28 -07:00
Alex Forencich	10357d97d4	Add BPI flash access and IPROG for VCU108	2020-10-02 20:44:47 -07:00
Alex Forencich	96f015d905	Update LED connections	2020-09-29 00:38:04 -07:00
Alex Forencich	70b7082fb6	Implement new control registers	2020-09-19 17:25:58 -07:00
Alex Forencich	c8f5bb235c	Remove extraneous clock connections	2020-08-19 18:33:41 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	9e3e80661c	Use common sync_reset module	2020-03-27 23:53:05 -07:00
Alex Forencich	a501f33c09	Update parameters	2019-12-29 16:46:25 -08:00
Alex Forencich	0955a4101f	Fix signal widths	2019-12-29 16:45:32 -08:00
Alex Forencich	7a68abbb84	Split control and data descriptor paths to DMA engine	2019-12-13 14:15:25 -08:00
Alex Forencich	88e31d0ccb	Connect PCIe credit interface to DMA cores	2019-12-13 12:41:50 -08:00
Alex Forencich	6270278c75	Add RSS support	2019-12-06 14:15:16 -08:00
Alex Forencich	0e7a91d927	Connect RQ sequence number	2019-12-03 18:19:17 -08:00
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	33be402b16	Update widths	2019-11-14 00:02:10 -08:00
Alex Forencich	f36773660d	Set flash ID	2019-11-06 15:05:32 -08:00
Alex Forencich	736321641f	Parametrize addressing	2019-10-31 23:24:42 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	9ab0d50c0a	Add PCIe interface tuser width parameters	2019-10-05 13:56:24 -07:00
Alex Forencich	9a1a58f608	Add PCIe interface tuser width parameters	2019-10-04 16:51:07 -07:00
Alex Forencich	835abf9412	Remove pcie_us_axi_master instances and corresponding BAR	2019-09-19 17:31:59 -07:00
Alex Forencich	b5868c8997	Update PTP perout support in VCU108 and VCU118 designs	2019-09-18 19:46:45 -07:00
Alex Forencich	132d44cd90	Increase crossbar threads count	2019-09-11 18:06:14 -07:00
Alex Forencich	d67c9ff70e	Pull out scheduler op table size parameter	2019-08-23 07:44:33 -07:00
Alex Forencich	744ac22c75	Normalize queue op table sizes	2019-08-22 19:19:51 -07:00
Alex Forencich	6a354e7aa3	Normalize descriptor table sizes	2019-08-22 19:03:19 -07:00
Alex Forencich	2fbbfb05f9	Parametrize channel assignments	2019-07-28 16:02:54 -07:00
Alex Forencich	26f6774182	Parameter updates and documentation	2019-07-27 23:47:46 -07:00
Alex Forencich	958aec8e8c	Add VCU108 mqnic design	2019-07-25 17:05:56 -07:00