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47 Commits

Author SHA1 Message Date
Alex Forencich
f9eda00d68 Use quad wrappers in ExaNIC X10 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:43:29 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
d6fc68947b Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 20:25:08 -07:00
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 15:07:45 -08:00
Alex Forencich
7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 14:57:46 -08:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
38e3244caa Rework GT instances in ExaNIC X10 design 2021-10-18 00:34:06 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
c021d01c26 Update example design readmes 2021-05-04 15:48:12 -07:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
ed7136a095 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:27:30 -07:00
Alex Forencich
6aba3a741a Update makefiles 2020-08-06 17:19:11 -07:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
b7c089dd22 XDC clean up 2020-07-13 23:58:30 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
b3c654461e Update example design 2019-10-22 23:17:39 -07:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
386ff91210 Add ExaNIC X10 flash programming commands 2019-06-27 01:27:32 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
cfcd9da375 Update IP 2019-06-26 20:50:05 -07:00
Alex Forencich
15b3aaf2e7 Update programming commands 2019-06-26 20:17:45 -07:00
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
5f6e7f721c Update testbench 2019-01-31 18:12:07 -08:00
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
6d52a7c0e7 Remove unneeded links 2019-01-08 17:31:49 -08:00
Alex Forencich
1f793fa7d0 Update readme 2019-01-08 17:24:22 -08:00
Alex Forencich
82454e4ae1 Add ExaNIC X10 example design 2019-01-08 17:22:01 -08:00