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Author SHA1 Message Date
Alex Forencich
a2ce454c22 Add log_desc_block_size to driver 2020-04-21 14:38:21 -07:00
Alex Forencich
9e64d19ea5 Use scatter descriptor blocks in driver model 2020-04-21 01:04:07 -07:00
Alex Forencich
2c6e9673f7 Add log_desc_block_size ring parameter in driver model 2020-04-21 00:58:12 -07:00
Alex Forencich
e14cfa0a58 Update port and interface modules 2020-04-20 21:25:21 -07:00
Alex Forencich
7087a595e9 Update RX and TX engines to support descriptor blocks 2020-04-20 21:24:25 -07:00
Alex Forencich
0fb60d718d Add log desc block size to desc_fetch module 2020-04-20 21:01:55 -07:00
Alex Forencich
d0cf549057 Add log desc block size field to queue manager 2020-04-20 20:45:10 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
4a50e1ec63 Add block diagram 2020-04-17 16:35:34 -07:00
Alex Forencich
33d82870c1 Add paper link 2020-04-10 11:20:19 -07:00
Alex Forencich
a195167056 Update title 2020-04-01 11:56:11 -07:00
Alex Forencich
4c41251570 Update readme 2020-03-28 00:49:03 -07:00
Alex Forencich
bffb9b7b19 Add board ID for NetFPGA SUME 2020-03-28 00:48:22 -07:00
Alex Forencich
105a834790 Add mqnic design for NetFPGA SUME 2020-03-28 00:44:04 -07:00
Alex Forencich
9e3e80661c Use common sync_reset module 2020-03-27 23:53:05 -07:00
Alex Forencich
c364bab778 merged changes in eth 2020-03-27 19:08:47 -07:00
Alex Forencich
73bd619d85 Add NetFPGA SUME example design 2020-03-27 19:01:50 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
12083439ac merged changes in axis 2020-03-27 18:04:39 -07:00
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00
Alex Forencich
3786cf0ca3 merged changes in pcie 2020-03-26 17:25:23 -07:00
Alex Forencich
6e974aca27 Driver update for Linux kernel API change 2020-03-26 16:12:56 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
0b559cebbf Published in FCCM 2020 2020-03-26 11:54:48 -07:00
Alex Forencich
ec03a36f98 Add 100G mqnic design for VCU118 2020-03-25 23:02:36 -07:00
Alex Forencich
309ee212bc merged changes in pcie 2020-03-24 23:25:56 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00
Alex Forencich
a196cd227c Enable bus mastering and MSI in driver model 2020-03-12 15:32:08 -07:00
Alex Forencich
457f4d7f3f Use configured ring stride 2020-03-12 15:28:00 -07:00
Alex Forencich
0c32192226 Use constants instead of magic numbers 2020-03-12 15:08:20 -07:00
Alex Forencich
559fc54ea5 Fix RX checksum offloading 2020-03-10 23:39:04 -07:00
Alex Forencich
3d959c2d4f Use configured ring stride 2020-03-10 23:07:30 -07:00
Alex Forencich
65ead3a064 Update receive handling to allocate pages instead of skbs 2020-03-10 23:06:54 -07:00
Alex Forencich
8536b7d2b7 Minor refactor of CQ processing 2020-03-10 22:06:02 -07:00
Alex Forencich
37294142b8 Rework DMA mapping 2020-03-09 17:21:39 -07:00
Alex Forencich
1216f7a76e Offset packet start by 10 bytes to match Linux kernel skb alignment 2020-03-08 21:56:08 -07:00
Alex Forencich
23aef37aff Rewrite resets 2020-03-08 16:56:06 -07:00
Alex Forencich
24eae58e6c merged changes in pcie 2020-03-08 15:25:28 -07:00
Alex Forencich
248a0b4f93 Convert descriptor to DMA operation without storing in table 2020-03-08 00:22:55 -08:00
Alex Forencich
f7a1a7ef95 Add descriptor FIFOs 2020-03-07 22:28:59 -08:00
Alex Forencich
4dd5104f4d Stripe completion queues across event queues 2020-03-06 00:58:30 -08:00
Alex Forencich
627153cd9b Fix signal sizing bug 2020-03-06 00:24:13 -08:00
Alex Forencich
060320010d Don't configure MSI if already configured 2020-03-02 21:16:09 -08:00
Alex Forencich
37934485af Timing optimization for ram_wrap computation 2020-02-28 13:22:35 -08:00
Alex Forencich
983610d6d9 Timing optimization for mask computation 2020-02-28 13:02:26 -08:00
Alex Forencich
50124ce66d Timing optimization 2020-02-28 01:01:37 -08:00
Alex Forencich
db4d0a8f94 Timing optimizations 2020-02-27 20:00:37 -08:00
Alex Forencich
092c72ba66 Compute req_last_tlp in advance 2020-02-27 18:19:45 -08:00
Alex Forencich
18bf537f4f Fix register size 2020-02-27 15:47:18 -08:00