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34 Commits

Author SHA1 Message Date
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
2779087de9 Constrain DMA muxes to same SLR 2021-02-23 02:17:10 -08:00
Alex Forencich
ceebb9f20e Add more PCIe-related components to PCIe pblock 2021-02-23 00:55:05 -08:00
Alex Forencich
ea093b0126 More XDC cleanup 2021-02-06 15:15:05 -08:00
Alex Forencich
24d179dd4a VCU118 XDC cleanup 2021-02-05 22:14:00 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
722bd929b8 Placement updates 2021-01-31 12:48:49 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
972e41e433 Update placement constraints 2021-01-14 22:06:24 -08:00
Alex Forencich
7ede1d38e6 Update placement constraints for VCU118 100G design 2021-01-14 16:50:21 -08:00
Alex Forencich
6476ad3fd0 Separate file for placement constraints 2021-01-14 14:42:58 -08:00
Alex Forencich
42e19e1e96 Add pipeline registers, floorplanning constraints for VCU118 100G design 2021-01-13 20:55:20 -08:00
Alex Forencich
c0c2f933c0 Rework sim_build output directory, fix default makefile target 2020-12-29 17:28:53 -08:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
ac4859d88e Fix user_clk_frequency setting in testbenches 2020-10-12 23:07:43 -07:00
Alex Forencich
d6810db7f5 Add extra output register for flash interface to improve routability and timing 2020-10-08 19:22:28 -07:00
Alex Forencich
993a712f01 Update VCU118 XDC 2020-10-06 00:41:45 -07:00
Alex Forencich
5ecfe4bcca Update flash programming configuration for VCU118 2020-10-05 17:12:45 -07:00
Alex Forencich
c2ded31ab7 Add QSPI flash access and IPROG for VCU118 2020-10-05 17:06:12 -07:00
Alex Forencich
96f015d905 Update LED connections 2020-09-29 00:38:04 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
e54eb685b3 Update makefiles 2020-08-06 18:43:47 -07:00
Alex Forencich
77b9cace47 Update BAR configuration in testbenches 2020-07-28 19:01:53 -07:00
Alex Forencich
ffd04d2bb0 Cleanup 2020-07-28 19:00:33 -07:00
Alex Forencich
d449be8fc5 Convert to 64 bit BARs 2020-07-24 16:54:57 -07:00
Alex Forencich
837a390567 Fix VCU118 CMAC reference clocks 2020-07-14 10:47:18 -07:00
Alex Forencich
e230fecb23 XDC clean up 2020-07-13 23:58:39 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
9e3e80661c Use common sync_reset module 2020-03-27 23:53:05 -07:00
Alex Forencich
ec03a36f98 Add 100G mqnic design for VCU118 2020-03-25 23:02:36 -07:00