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13 Commits

Author SHA1 Message Date
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
46149bef3f Update ZCU106 XDC 2021-02-05 22:22:25 -08:00
Alex Forencich
b16fe8f7e7 More XDC clean up, add IO delay constraints for low speed IO 2021-02-05 16:08:23 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
c0c2f933c0 Rework sim_build output directory, fix default makefile target 2020-12-29 17:28:53 -08:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
ac4859d88e Fix user_clk_frequency setting in testbenches 2020-10-12 23:07:43 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
f8dca522a1 Add missing symlink 2020-08-20 12:26:24 -07:00
Alex Forencich
e6b35f0567 Add PCIe mqnic design for ZCU106 2020-08-06 23:25:23 -07:00