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181 Commits

Author SHA1 Message Date
Alex Forencich
a44f9852c2 Update Stratix 10 H-tile/L-tile shim to support segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:48:46 -07:00
Alex Forencich
5658af86e0 Add PCIe TLP FIFO mux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:41:27 -07:00
Alex Forencich
cc1278f9d9 Update PCIe TLP mux to handle multiple segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:40:35 -07:00
Alex Forencich
23705eb873 Update PCIe TLP demux to handle segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:39:38 -07:00
Alex Forencich
fc42368bd5 Add segmented PCIe TLP FIFO module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:35:57 -07:00
Alex Forencich
1ca13c3af2 Add TLP mux and demux tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 01:06:29 -07:00
Alex Forencich
d1e21cb78b Add shim stress tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-12 23:30:27 -07:00
Alex Forencich
58d705b924 Add channel testbenches for S10 shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:50:38 -07:00
Alex Forencich
07970ae41d Add channel testbenches for UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:13:21 -07:00
Alex Forencich
27f749d5a5 Add strobe outputs to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-07 14:23:24 -07:00
Alex Forencich
52e7af8a5d Add combined TX/RX bus with all signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 19:09:15 -07:00
Alex Forencich
aadcd53c87 Update AXI DMA IF tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:29:16 -07:00
Alex Forencich
7d92722fe8 Clean up testbench parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:25:28 -07:00
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
ee59fc10e0 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:26:27 -07:00
Alex Forencich
87bf5f2e41 Properly implement zero-length operations in generic interface model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-04 14:52:54 -07:00
Alex Forencich
5208b2844c Add MSI-X support to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:35:34 -07:00
Alex Forencich
2fa0bf3eb0 Add MSI-X module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:34:15 -07:00
Alex Forencich
ba5188dd93 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:33:52 -07:00
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
7cae50fa10 Support zero-length operations in AXI DMA interface modules 2022-03-30 23:40:02 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Alex Forencich
2c3a5f4bda Update testbenches 2021-11-17 17:21:35 -08:00
Alex Forencich
63e7df0044 Fix makefile 2021-11-17 16:43:27 -08:00
Alex Forencich
78badc447f Update pcie_if model 2021-11-17 01:00:24 -08:00
Alex Forencich
e898f7bdc2 Accept any completion status-related DMA error 2021-11-16 00:54:52 -08:00
Alex Forencich
0d1af9ba55 Use correct completer IDs 2021-11-16 00:44:36 -08:00
Alex Forencich
6cafb46c49 Include TLP in log messages 2021-11-16 00:33:44 -08:00
Alex Forencich
5b528158df Remove deprecated assignments 2021-11-09 11:55:12 -08:00
Alex Forencich
8a7f410aaf Don't read address/data if valid is not set 2021-11-07 19:03:10 -08:00
Alex Forencich
5c5876ff1d Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile 2021-11-02 22:29:57 -07:00
Alex Forencich
482b305913 Fix 64-bit TLP address forcing logic in generic interface model 2021-10-27 17:54:41 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00
Alex Forencich
cb6b15cae0 Reset error signal monitor 2021-10-03 12:17:57 -07:00
Alex Forencich
85b8231abf Add IO operations to bad ops test for pcie_axil_master_minimal 2021-10-03 11:47:45 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
85391d2b9b Compare all fields 2021-08-20 14:10:03 -07:00
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00
Alex Forencich
f8f95a214b Set completer ID in testbench 2021-08-04 17:08:25 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00