14 Commits

Author	SHA1	Message	Date
Alex Forencich	27f749d5a5	Add strobe outputs to shims ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-07 14:23:24 -07:00
Alex Forencich	52e7af8a5d	Add combined TX/RX bus with all signals ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-05 19:09:15 -07:00
Alex Forencich	87bf5f2e41	Properly implement zero-length operations in generic interface model ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-04 14:52:54 -07:00
Alex Forencich	5208b2844c	Add MSI-X support to shims ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-02 23:35:34 -07:00
Alex Forencich	bac4e4066f	Use start_soon instead of fork	2021-12-10 17:44:37 -08:00
Alex Forencich	78badc447f	Update pcie_if model	2021-11-17 01:00:24 -08:00
Alex Forencich	0d1af9ba55	Use correct completer IDs	2021-11-16 00:44:36 -08:00
Alex Forencich	6cafb46c49	Include TLP in log messages	2021-11-16 00:33:44 -08:00
Alex Forencich	5b528158df	Remove deprecated assignments	2021-11-09 11:55:12 -08:00
Alex Forencich	482b305913	Fix 64-bit TLP address forcing logic in generic interface model	2021-10-27 17:54:41 -07:00
Alex Forencich	f2f19f7174	Update terminology, use byte_lanes instead of byte_width	2021-09-25 22:52:19 -07:00
Alex Forencich	85391d2b9b	Compare all fields	2021-08-20 14:10:03 -07:00
Alex Forencich	7fed6876a3	Init seq to 0	2021-08-11 19:52:47 -07:00
Alex Forencich	623cc1ae8d	Add generic PCIe interface model	2021-08-03 22:33:23 -07:00