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2239 Commits

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Author SHA1 Message Date
Alex Forencich
2adaf820b5 More kernel module coding style updates 2021-10-21 13:54:00 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
dc0c5a17ff merged changes in pcie 2021-10-20 19:32:15 -07:00
Alex Forencich
87aca91fd9 merged changes in eth 2021-10-20 19:32:09 -07:00
Alex Forencich
e8359741f5 merged changes in axi 2021-10-20 19:32:04 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
9ff4454db0 Update makefiles 2021-10-20 17:21:58 -07:00
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
1e6d667ae0 merged changes in axis 2021-10-20 15:36:38 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00
Alex Forencich
302a23209f Add missing wires 2021-10-20 13:00:44 -07:00
Alex Forencich
786eabac4b Add missing wires 2021-10-20 02:01:33 -07:00
Alex Forencich
9f6f388a3c Rework GT instances in HTG9200 design 2021-10-20 00:57:11 -07:00
Alex Forencich
527c2f1b89 Rework GT instances in fb2CG@KU15P design 2021-10-20 00:56:13 -07:00
Alex Forencich
05770c5a1b Rework GT instances in VCU118 designs 2021-10-19 22:13:02 -07:00
Alex Forencich
531f751e67 Update VCU118 XDC 2021-10-19 22:11:56 -07:00
Alex Forencich
cf016dc4ee Rework GT instances in VCU108 design 2021-10-19 22:11:34 -07:00
Alex Forencich
1f76eb4534 Update VCU108 XDC 2021-10-19 22:10:32 -07:00
Alex Forencich
a1da0ba184 Rework GT instances in VCU1525 design 2021-10-19 18:40:32 -07:00
Alex Forencich
0b41dc4011 Rework GT instances in ZCU102 design 2021-10-19 18:38:22 -07:00
Alex Forencich
e3f8879474 Rework GT instances in ZCU106 design 2021-10-19 18:30:35 -07:00
Alex Forencich
4ce218bc5d Rework GT instances in ADM-PCIE-9V3 designs 2021-10-19 18:29:18 -07:00
Alex Forencich
21da6f58dc Rework GT instances in Alveo U280 design 2021-10-19 18:28:10 -07:00
Alex Forencich
4fdc6408bc Rework GT instances in Alveo U50 design 2021-10-19 18:14:50 -07:00
Alex Forencich
cc4256666a Rework GT instances in Alveo U250 design 2021-10-19 17:47:15 -07:00
Alex Forencich
f11f7ecac9 Rework GT instances in Alveo U200 design 2021-10-19 17:45:43 -07:00
Alex Forencich
38e3244caa Rework GT instances in ExaNIC X10 design 2021-10-18 00:34:06 -07:00
Alex Forencich
fa77fe54f3 Rework GT instances in ExaNIC X25 design 2021-10-18 00:32:37 -07:00
Alex Forencich
0a6665cada merged changes in eth 2021-10-17 22:55:09 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
45ddd70036 merged changes in axis 2021-10-17 01:42:17 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic 2021-10-16 01:25:48 -07:00
Alex Forencich
247aeae845 Detect bad XGMII encodings in PHY TX 2021-10-16 00:50:48 -07:00
Alex Forencich
3b2e6874d8 Rework XGMII to BASE-R encoder implementation 2021-10-16 00:48:01 -07:00
Alex Forencich
9667ef1f9c Detect sequence errors 2021-10-16 00:03:35 -07:00
Alex Forencich
5258bdc312 Improve bad block detection 2021-10-15 23:58:35 -07:00
Alex Forencich
571394f99f Translate LPI control characters 2021-10-15 23:53:53 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules 2021-10-15 01:37:10 -07:00
Alex Forencich
e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules 2021-10-15 01:08:14 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00