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mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00

2239 Commits

Author SHA1 Message Date
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
c8dd50b051 pcie_print_link_status was added in kernel version 4.17 2021-09-24 17:05:35 -07:00
Alex Forencich
39fbc194fd Update makefiles 2021-09-20 18:22:47 -07:00
Alex Forencich
52ba4c40e2 Update readme 2021-09-13 20:40:39 -07:00
Alex Forencich
1bee717bc8 Remove old TDMA variants 2021-09-13 17:20:44 -07:00
Alex Forencich
cc6348653d Add TDMA variants 2021-09-13 17:19:50 -07:00
Alex Forencich
620791e562 Add TDMA testbench 2021-09-13 17:11:39 -07:00
Alex Forencich
df9417454e Improve messages 2021-09-13 16:18:11 -07:00
Alex Forencich
4704115974 Allow boot and reset even if flashing is not supported 2021-09-13 16:17:55 -07:00
Alex Forencich
3d64e5fc30 Retry hot reset a few times if necessary 2021-09-13 13:51:36 -07:00
Alex Forencich
5435db91cb Ensure that boot/reset are skipped if flash update fails 2021-09-13 13:51:06 -07:00
Alex Forencich
dfe0dd38f0 Print out mismatches when verify fails 2021-09-13 13:50:27 -07:00
Alex Forencich
9da588cf73 Add dummy reads for timing 2021-09-13 13:49:29 -07:00
Alex Forencich
e8c28e00cd Update tox configuration 2021-09-13 13:02:17 -07:00
Alex Forencich
f25cfa0982 Update tox configuration 2021-09-13 13:00:03 -07:00
Alex Forencich
875b664c13 Update offset 2021-09-13 12:54:35 -07:00
Alex Forencich
b0bb8d628a Update tox configuration 2021-09-13 01:38:16 -07:00
Alex Forencich
b1596751cf Update NetFPGA SUME design 2021-09-13 01:30:36 -07:00
Alex Forencich
f66f4d7cce Update VCU118 designs 2021-09-13 00:09:23 -07:00
Alex Forencich
bfea350194 Update VCU108 design 2021-09-12 23:17:50 -07:00
Alex Forencich
58a2dbd734 Update ZCU106 design 2021-09-12 23:17:01 -07:00
Alex Forencich
3f8becb186 Update ExaNIC X10 design 2021-09-12 21:56:33 -07:00
Alex Forencich
a18eced17f Update ExaNIC X25 design 2021-09-12 12:40:39 -07:00
Alex Forencich
49a2b6462f Update ADM-PCIE-9V3 designs 2021-09-11 23:22:08 -07:00
Alex Forencich
200ef77b09 Update VCU1525 designs 2021-09-11 20:07:32 -07:00
Alex Forencich
d7e9e91644 Fix FIFO size parameter defaults 2021-09-11 17:42:24 -07:00
Alex Forencich
26fdddb3ae Update Alveo U250 designs 2021-09-11 01:27:23 -07:00
Alex Forencich
ec89492d24 Fix control register addressing bug 2021-09-11 00:49:48 -07:00
Alex Forencich
ed418f101a Update Alveo U200 designs 2021-09-10 23:40:53 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00
Alex Forencich
079ad5ec37 Add pblock for 10G MACs 2021-09-10 18:52:46 -07:00
Alex Forencich
9ee5463b92 Remove blank line 2021-09-10 18:52:22 -07:00
Alex Forencich
6a44a59b2c Move LED assignments 2021-09-10 10:53:41 -07:00
Alex Forencich
ada43236d9 Fix alignment 2021-09-09 23:17:52 -07:00
Alex Forencich
c56f6d717b Fix IDs 2021-09-09 22:05:27 -07:00
Alex Forencich
c92dbfe7ed Update file lists 2021-09-09 21:52:16 -07:00
Alex Forencich
fcf4bc007f Update Alveo U280 designs 2021-09-09 18:09:08 -07:00
Alex Forencich
2442ff65c5 Support application and RAM bars 2021-09-09 17:50:44 -07:00
Alex Forencich
d0976f193b Use correct type 2021-09-09 17:49:11 -07:00
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00
Alex Forencich
371717b854 Add block names 2021-09-09 14:12:41 -07:00
Alex Forencich
b097aa5c9e merged changes in pcie 2021-09-09 01:00:10 -07:00
Alex Forencich
b131b2ebbf Rework DMA desc status demux to fix X issue at t=0 2021-09-09 00:58:48 -07:00
Alex Forencich
97e3daa36c Extract information from design instead of env vars 2021-09-08 16:44:58 -07:00
Alex Forencich
c920272e84 Use interface address widths directly instead of BAR size parameters 2021-09-08 14:51:18 -07:00
Alex Forencich
3cbb4a9506 merged changes in pcie 2021-09-08 10:05:40 -07:00
Alex Forencich
f566df2c66 Add TLP mux and demux modules 2021-09-08 10:04:38 -07:00
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
c00a53155d Fix alignment 2021-09-07 01:38:09 -07:00