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Author SHA1 Message Date
Alex Forencich
a54b673d54 Explicitly set equalizer mode 2022-03-02 23:11:49 -08:00
Alex Forencich
348aae9687 Update fb2CG@KU15P designs to use new wrapper 2022-03-02 17:38:47 -08:00
Alex Forencich
e91de95955 Fix rb_drp timing constraint for write enable signal 2022-03-02 17:31:17 -08:00
Alex Forencich
90d28ec9a2 Add common 10G PHY + GTH/GTY transceiver wrapper module 2022-03-02 17:28:40 -08:00
Alex Forencich
c799db69b4 Add PROGDIV_RATE register value defines 2022-03-02 17:26:02 -08:00
Alex Forencich
1378444d0c Add GTH and GTY transceiver DRP register definitions 2022-02-23 21:09:06 -08:00
Alex Forencich
614b391c48 Add DRP register block 2022-02-21 23:20:54 -08:00
Alex Forencich
65fbad93ca Fix parameter defaults 2022-02-20 00:13:35 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
1e4a88dea9 merged changes in pcie 2022-02-15 01:59:21 -08:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
a65b256b85 Update default SEG_ADDR_WIDTH parameter value for DMA RAM 2022-02-14 22:28:50 -08:00
Alex Forencich
66708ed6ff Add some more parameter checks 2022-02-14 00:41:28 -08:00
Alex Forencich
c98258bf05 Fix parametrization 2022-02-13 23:19:09 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
01f0631ddb Update parameters 2022-02-11 22:04:04 -08:00
Alex Forencich
69ec8a9b52 merged changes in pcie 2022-02-03 00:58:24 -08:00
Alex Forencich
defdbb14df merged changes in axi 2022-02-03 00:58:18 -08:00
Alex Forencich
440e6a06a2 merged changes in eth 2022-02-03 00:57:55 -08:00
Alex Forencich
6e716af299 Set PTP clock name 2022-02-02 18:41:19 -08:00
Alex Forencich
c47332462d Implement USE_AXI_ID for dma_if_axi_rd 2022-02-01 16:29:56 -08:00
Alex Forencich
27f90934fe Refactor to use existing variable 2022-02-01 16:27:13 -08:00
Alex Forencich
a0a7732801 Add missing resets 2022-02-01 16:26:12 -08:00
Alex Forencich
2f6ad1e28d Implement USE_AXI_ID for dma_if_axi_wr 2022-02-01 00:43:21 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
e86d47f667 Improve parameter handling in start_xmit 2022-01-27 23:42:32 -08:00
Alex Forencich
155aa5caae Block in start_xmit when ring is full 2022-01-27 23:34:38 -08:00
Alex Forencich
f98d831014 Ensure that info ring location is empty when sending packets 2022-01-27 23:21:32 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
36bd1f78b0 Add missing parameter connection in rx_fifo 2022-01-26 09:44:35 -08:00
Alex Forencich
2132a8d98f Fix index handling in driver model 2022-01-26 09:30:41 -08:00
Alex Forencich
74e4322d43 Fix bug in example design core logic 2022-01-17 21:45:49 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
d506c9305a Fix pointer updating for correct teardown behavior 2022-01-16 00:04:53 -08:00
Alex Forencich
137a6778da Combine interface control blocks 2022-01-15 21:53:13 -08:00
Alex Forencich
0f82e0c5f3 Fix ethtool firmware version number reporting 2022-01-10 11:18:58 -08:00
Alex Forencich
eba32ce8a5 Accept interface name and PCIe BDF when connecting to device 2022-01-08 15:32:50 -08:00
Alex Forencich
23f635f273 Clean up return code checks 2022-01-08 15:14:49 -08:00
Alex Forencich
136b0ee6ae Increase init delay for Alveo BMC 2022-01-05 22:42:36 -08:00
Alex Forencich
a4a26e7bc4 Fix register accesses 2022-01-05 19:38:56 -08:00
Alex Forencich
975ba91239 Fix register accesses 2022-01-05 19:38:46 -08:00
Alex Forencich
7d8b5560b7 Fix backpressure bug 2021-12-31 22:58:38 -08:00
Alex Forencich
853c1737aa Simplify logic 2021-12-31 22:57:11 -08:00
Alex Forencich
ddd7e639da Add tdest register to scheduler blocks 2021-12-31 17:02:59 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
6163efa0b8 Add output pipeline stage to descriptor FIFOs 2021-12-29 14:30:05 -08:00
Alex Forencich
2091ef8c42 Fix dev_port assignment 2021-12-29 14:29:55 -08:00
Alex Forencich
dc247259fd Update tox.ini 2021-12-28 20:29:40 -08:00