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3 Commits

Author SHA1 Message Date
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00