16 Commits

Author	SHA1	Message	Date
Alex Forencich	a613cc8a31	Fix alignment	2021-08-25 23:58:52 -07:00
Alex Forencich	4fa3870dea	Remove string parameters	2021-06-02 15:08:43 -07:00
Alex Forencich	16b174b490	Print addressing configuration	2021-05-30 12:19:01 -07:00
Alex Forencich	56a3b8fe92	Fix indexed part select error in degenerate case when M_COUNT = 1	2021-05-30 12:11:46 -07:00
Alex Forencich	ce00df8de1	Include instance names in error messages	2019-07-25 16:30:10 -07:00
Alex Forencich	0a85a4a2aa	Fix assert	2019-07-25 00:43:42 -07:00
Alex Forencich	592ae7e6a2	Change default switch addressing to use MSBs of tdest	2019-07-25 00:40:13 -07:00
Alex Forencich	76c805e416	Fix more indexing bugs	2019-07-24 15:38:49 -07:00
Alex Forencich	23b9490fac	Fix switch bug	2019-07-24 15:22:35 -07:00
Alex Forencich	5f454d6c05	Update axis_switch to support default routing configurations	2019-07-24 14:20:07 -07:00
Alex Forencich	c5f44c70d1	Add parameter documentation	2019-07-24 13:54:21 -07:00
Alex Forencich	c759ff03b7	Fix default parameter	2019-07-24 11:07:17 -07:00
Alex Forencich	a9c7946368	Change parameter concatenation to increments of DEST_WIDTH	2019-03-28 23:49:04 -07:00
Alex Forencich	145ea2c40c	Connect arbiter parameters to top level	2018-10-24 21:09:00 -07:00
Alex Forencich	029d1fa06f	Fix loop count variable scoping issue	2018-10-24 17:58:39 -07:00
Alex Forencich	fd7f65d5ad	Convert generated switch to verilog parametrized switch	2018-10-24 16:12:56 -07:00