7 Commits

Author	SHA1	Message	Date
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	8985c6dbf3	Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules	2019-12-03 15:46:36 -08:00
Alex Forencich	80dafd5870	Check FIFO depth	2019-12-02 15:15:24 -08:00
Alex Forencich	2dbe6e19ab	Reset mask FIFO pointers	2019-12-02 14:07:17 -08:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	89ff925545	Timing optimizations	2019-10-14 14:00:55 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00