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Author SHA1 Message Date
Alex Forencich
0b8a36d5e7 Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
d82ebcce17 Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
a2a509884e Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
c86ffa1202 Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
47a8c35d5d Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
a9bbdae908 Improve output register filling 2014-10-22 15:10:07 -07:00
Alex Forencich
a92eb4e57f Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
2cf95840ee Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
7e01c6c14c Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
3b1655f81f Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
63843e9d5d Update rate limit test bench to check more settings and verify rate 2014-10-21 23:25:28 -07:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
09d0d87939 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
8e9b38cde0 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
8bce338bc0 Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
2495dd2bac Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
2ec83046f6 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
f53f4aa504 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
ca50423036 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
6ab2a86e13 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00
Alex Forencich
e14a79dee4 Add IP module and testbench 2014-09-29 22:26:55 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00
Alex Forencich
20da100db6 Add UDP transmit and receive modules 2014-09-25 16:52:42 -07:00
Alex Forencich
0f1eb94148 Calculate header checksum for truncated packets 2014-09-25 16:26:59 -07:00
Alex Forencich
ebc1c7ccc6 Rename checksum to calc_checksum in ip_ep 2014-09-25 16:26:23 -07:00
Alex Forencich
8191b38e7a Move header valid assign to top 2014-09-25 16:25:37 -07:00
Alex Forencich
c6236bc647 Add 64-bit datapath version of IP modules 2014-09-25 00:40:48 -07:00
Alex Forencich
3bee612dfd Add extra delays to IP testbenches 2014-09-25 00:39:22 -07:00
Alex Forencich
d052bbb2bf Update 64-bit ethernet modules with lane shifting logic 2014-09-25 00:38:36 -07:00
Alex Forencich
ac57a22050 Abort with early termination error on last assert on first header word 2014-09-25 00:37:14 -07:00
Alex Forencich
33a61d8d89 Rework Ethernet module testbenches 2014-09-25 00:36:08 -07:00
Alex Forencich
5eaba1c3b3 Do not clock out a header if the last signal falls on the last word 2014-09-24 23:52:41 -07:00
Alex Forencich
c9a2b89717 Remove unused register 2014-09-24 01:12:48 -07:00
Alex Forencich
3fdd453e0f Rework IP module testbenches 2014-09-21 15:56:12 -07:00
Alex Forencich
c74d2d1127 Update comment 2014-09-21 15:55:02 -07:00
Alex Forencich
119958cccb Remove unused parameter 2014-09-21 15:54:54 -07:00
Alex Forencich
4d012b4f52 Properly reset everything 2014-09-21 15:53:59 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00
Alex Forencich
4ad302949f Add defaults 2014-09-19 17:33:23 -07:00
Alex Forencich
54bc201f52 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
fa72cc2035 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
2fd2663eee Update comments 2014-09-19 17:31:34 -07:00
Alex Forencich
fdb31878e9 Remove length fields from ARP transmit module 2014-09-17 12:36:56 -07:00
Alex Forencich
33c044e035 Add invalid header and tuser assert checks and tests 2014-09-15 19:31:10 -07:00