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7 Commits

Author SHA1 Message Date
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
39200d84cb Update simulation models to support 512 bit interface 2019-10-14 15:45:41 -07:00
Alex Forencich
9b5a5db4d1 Add USPcieFrame intermediate format 2019-10-12 18:01:39 -07:00
Alex Forencich
1b91200a4a Implement error code 2019-10-01 17:17:42 -07:00
Alex Forencich
f1348db2f7 Add Ultrascale Plus PCIe hard IP core model and testbench 2019-07-15 17:18:39 -07:00