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35 Commits

Author SHA1 Message Date
Alex Forencich
ca655ca9fb Update example designs based on results of buffer size tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-16 16:55:42 -07:00
Alex Forencich
b91076f6d3 Fix AXIS_PCIE_RQ_USER_WIDTH parameter for US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-13 11:28:20 -07:00
Alex Forencich
9cee4f3808 Update example designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 18:38:43 -07:00
Alex Forencich
c6c83a7c68 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:58:34 -08:00
Alex Forencich
9c5c6e6edf Rework parameter handling in example design makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:56:53 -08:00
Alex Forencich
91450fcab7 PCIe flow control is handled in shim; remove flow control from PCIe DMA interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 13:47:02 -07:00
Alex Forencich
3f334dbbbb Use MSI-X in example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 23:32:51 -07:00
Alex Forencich
e2588cd995 Clean up TCL scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 16:23:54 -07:00
Alex Forencich
a17c33e3c6 Update example designs to enable TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 01:31:15 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
ee59fc10e0 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:26:27 -07:00
Alex Forencich
ba5188dd93 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:33:52 -07:00
Alex Forencich
0b815522b0 Sync example design testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:55 -07:00
Alex Forencich
e4b1df0ddb Fix immediate enable register implementation in example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:21 -07:00
Alex Forencich
32b4f2cb1f Improve block operation tests 2022-04-04 15:21:25 -07:00
Alex Forencich
e7a83364d0 Update testbenches 2022-04-04 15:05:21 -07:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6920845989 Update example design testbenches 2021-11-17 17:21:57 -08:00
Alex Forencich
47a2570647 Set class code to memory controller, set subsystem ID based on board 2021-11-02 14:39:33 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
a7b669e22f Update makefiles 2021-10-01 02:39:15 -07:00
Alex Forencich
14c84088ee Reorganize driver code 2021-08-13 14:22:32 -07:00
Alex Forencich
e4508b242f Update example designs 2021-08-02 18:36:25 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
bdfeaa84ca Update testbenches 2021-03-06 20:06:23 -08:00
Alex Forencich
266fed8d20 Update example design file list 2021-02-28 19:35:35 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
633b47ef7f Update XDC files 2021-02-06 17:14:26 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
cabad17552 Migrate example design testbenches to cocotb 2020-12-18 22:10:32 -08:00
Alex Forencich
5546e40812 Fix user_clk_frequency setting in testbenches 2020-10-12 23:05:28 -07:00
Alex Forencich
3ce28df7e0 Update flash programming commands 2020-09-29 18:28:38 -07:00
Alex Forencich
c04ba2de2e Fix flash settings 2020-09-29 17:30:42 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00