Alex Forencich
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ca655ca9fb
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Update example designs based on results of buffer size tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-16 16:55:42 -07:00 |
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Alex Forencich
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b91076f6d3
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Fix AXIS_PCIE_RQ_USER_WIDTH parameter for US+ devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-13 11:28:20 -07:00 |
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Alex Forencich
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9cee4f3808
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Update example designs for RX completion buffer management
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-30 18:38:43 -07:00 |
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Alex Forencich
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91450fcab7
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PCIe flow control is handled in shim; remove flow control from PCIe DMA interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 13:47:02 -07:00 |
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Alex Forencich
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3f334dbbbb
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Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-12 23:32:51 -07:00 |
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Alex Forencich
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a17c33e3c6
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Update example designs to enable TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 01:31:15 -07:00 |
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Alex Forencich
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12fea955d2
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Add example design for Alveo U250
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2021-11-18 16:26:43 -08:00 |
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