Alex Forencich
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1a4692bf17
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Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-10 14:51:36 -07:00 |
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Alex Forencich
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6bfaef78bd
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Properly handle 4KB read requests in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 21:52:27 -07:00 |
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Alex Forencich
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5e396ceb87
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Rename seg_rc_hdr to seg_rq_hdr
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 21:19:48 -07:00 |
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Alex Forencich
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0d9b1d0fb0
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Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-26 14:01:00 -07:00 |
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Alex Forencich
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19b1af0388
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Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 00:46:07 -07:00 |
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Alex Forencich
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70dc92c24e
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Rework TLP interface parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:27:04 -07:00 |
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Alex Forencich
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90959b8795
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Add default_nettype none and resetall directives
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2021-10-20 17:49:30 -07:00 |
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Alex Forencich
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836d14bad6
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Add PCIe interface shim for Xilinx UltraScale
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2021-08-04 01:03:31 -07:00 |
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