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252 Commits 1 Branch 0 Tags
Commit Graph

176 Commits

Author SHA1 Message Date
Alex Forencich
ae10935a93 Rewrite priority encoder to remove recusive construction 2020-08-17 18:29:05 -07:00
Alex Forencich
4754d94736 Fix backpressure bug 2020-04-17 21:22:07 -07:00
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00
Alex Forencich
f9915b2f31 Refactor 2020-02-19 21:32:00 -08:00
Alex Forencich
406a3d69d1 Rework read handling 2020-02-19 21:24:15 -08:00
Alex Forencich
2876235a72 Throughput optimizations 2020-02-19 18:15:58 -08:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
6795c25e7f Fix use before define 2019-08-09 18:05:32 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
0a85a4a2aa Fix assert 2019-07-25 00:43:42 -07:00
Alex Forencich
592ae7e6a2 Change default switch addressing to use MSBs of tdest 2019-07-25 00:40:13 -07:00
Alex Forencich
76c805e416 Fix more indexing bugs 2019-07-24 15:38:49 -07:00
Alex Forencich
23b9490fac Fix switch bug 2019-07-24 15:22:35 -07:00
Alex Forencich
5f454d6c05 Update axis_switch to support default routing configurations 2019-07-24 14:20:07 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
c091f7ed76 Add switch wrapper generator 2019-07-24 13:46:33 -07:00
Alex Forencich
b4cebd8394 Fix crosspoint wrapper generator 2019-07-24 13:44:43 -07:00
Alex Forencich
c759ff03b7 Fix default parameter 2019-07-24 11:07:17 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
e0a1a73ce0 Mask tdata with tkeep 2019-07-18 11:01:00 -07:00
Alex Forencich
ccc15324a6 Fix bad frame mask 2019-06-09 18:46:49 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00
Alex Forencich
a9c7946368 Change parameter concatenation to increments of DEST_WIDTH 2019-03-28 23:49:04 -07:00
Alex Forencich
932aa35451 Fix AXI stream async frame FIFO write pointer synchronization 2019-03-26 18:45:54 -07:00
Alex Forencich
88badf13f0 Reset all status synchronization stages 2019-03-26 16:19:49 -07:00
Alex Forencich
414f091c2c Properly handle width of 1 2019-03-07 22:59:49 -08:00
Alex Forencich
b1f3a74b86 Remove unused code 2019-03-07 22:59:15 -08:00
Alex Forencich
d2df971fc9 Add AXI stream frame length measurement module and testbenches 2019-03-07 22:57:46 -08:00
Alex Forencich
b60886a0ec Add AXI stream broadcast module and testbench 2019-02-27 19:46:30 -08:00
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
f45a3ef5e0 Change cycle to segment 2018-12-03 12:40:06 -08:00
Alex Forencich
a72d7bd260 Fix generate statement 2018-11-28 14:18:09 -08:00
Alex Forencich
8d564b1074 Convert localparam to parameter as Vivado does not like clog2 in localparams 2018-10-30 17:35:38 -07:00
Alex Forencich
be51f2b472 Update FIFO instantiations 2018-10-25 16:06:32 -07:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
ed4a2d73c2 Add axis_pipeline_register module 2018-10-25 14:29:35 -07:00
Alex Forencich
312d90addb Add wrapper generators 2018-10-25 14:23:00 -07:00
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
6f4ab8f180 Rename ports 2018-10-25 11:59:13 -07:00
Alex Forencich
84a758f100 Rename ports 2018-10-25 11:56:52 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
7997a4a844 Rename ports 2018-10-25 11:19:28 -07:00
Alex Forencich
8d9da455cd Minor optimizations 2018-10-25 10:29:31 -07:00
Alex Forencich
cb9f2132a4 Update parameter ordering 2018-10-25 10:20:17 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00