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176 Commits

Author SHA1 Message Date
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
4f66059d21 Adjust constant naming 2016-06-27 11:27:04 -07:00
Alex Forencich
f89620008d Remove reset dependence 2016-06-27 11:26:15 -07:00
Alex Forencich
cab7d367f2 Fix default width 2016-06-27 11:24:36 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
7a9fdb5fc3 Add default case statements to avoid inferring latches 2015-11-09 14:54:14 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
0a79f24d3c Do not reset datapath registers in crosspoint switch 2015-11-08 17:27:13 -08:00
Alex Forencich
5fb4cb159b Reorganize register modules 2015-11-08 16:18:29 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
7ea566e6d2 Update generate scripts to use argparse 2015-10-19 19:15:38 -07:00
Alex Forencich
dcad442e7c Improve timing performance of frame length adjust module 2015-10-19 00:30:50 -07:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00
Alex Forencich
382226ad59 Don't accept data until reset is complete 2015-10-08 23:46:59 -07:00
Alex Forencich
90ac361df5 Internal synchronous reset on async FIFOs 2015-10-08 13:03:42 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
26b165227c Update for compatibility with older versions of Python 2015-07-14 08:27:49 -07:00
Alex Forencich
ac97cffc2b Properly reset all registers 2015-07-13 23:15:09 -07:00
Alex Forencich
dfab866e99 Remove unused reg 2015-07-13 23:09:02 -07:00
Alex Forencich
04e4ccc517 Update for compatibility with older version of Python 2015-07-09 11:25:49 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
6bd7309b9d Properly reset all registers 2015-07-09 11:11:32 -07:00
Alex Forencich
87fe1a561f Add AXI stream tap modules 2015-06-22 14:56:56 -07:00
Alex Forencich
c15761068a Add AXI stream frame length adjust modules 2015-06-05 17:04:10 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
51e65f5a22 Rework async FIFO resets and synchronization 2015-05-08 01:41:35 -07:00
Alex Forencich
9cca78bc7c Fix last cycle detect logic 2015-04-19 23:33:34 -07:00
Alex Forencich
7795a9182b Remove tristate for state machine inference 2015-04-19 23:08:41 -07:00
Alex Forencich
966e47a826 Fix RAM and register widths 2015-04-19 23:06:30 -07:00
Alex Forencich
9b7bad92f2 Reset pointers correctly 2015-04-19 17:51:27 -07:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
3c7e3b0424 Add SRL register module and testbench 2014-12-03 18:51:46 -08:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00
Alex Forencich
b83dd34185 Fix register names 2014-12-03 13:15:13 -08:00
Alex Forencich
fbcbbe3a69 Remove adder tree 2014-11-21 10:43:20 -08:00
Alex Forencich
63f6e96492 Add tuser signal to crosspoint module 2014-11-21 01:07:02 -08:00
Alex Forencich
27cb9609f1 clog2 does not work in localparam in XST 2014-11-21 01:06:24 -08:00
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
0c3af7d5bb Reverse priority in arbitrated mux 2014-11-16 02:00:27 -08:00
Alex Forencich
d193ca5905 Add LSB_PRIORITY parameter 2014-11-16 01:58:17 -08:00
Alex Forencich
b123525597 Add enable signal 2014-11-16 01:38:20 -08:00
Alex Forencich
7c86999399 Minor reorganization 2014-11-13 16:26:07 -08:00
Alex Forencich
789c7da6d6 Fix parameter 2014-11-13 10:39:41 -08:00
Alex Forencich
698234c297 Update comments 2014-11-13 10:39:27 -08:00
Alex Forencich
851aeb9309 Fix block parameter 2014-11-13 10:06:28 -08:00
Alex Forencich
5f0d23a3ad Add AXI arbitrated mux module and testbench 2014-11-13 02:01:45 -08:00
Alex Forencich
a8970e6e75 Change block parameter 2014-11-13 02:01:07 -08:00
Alex Forencich
a1633f27d8 Add arbiter module 2014-11-13 01:22:59 -08:00