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3 Commits

Author SHA1 Message Date
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
e0167eedd8 Add AXI DMA interface modules and testbenches 2021-10-20 13:04:17 -07:00