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94 Commits

Author SHA1 Message Date
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
814a51a37c Use 128 KB RX RAM size for 25G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:24:56 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
18d5c325bf Fix CMAC RX PTP timestamps 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 23:21:11 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
f67c704b11 Update placement constraints for hierarchy changes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-02 13:16:20 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
eb530475fb More expressive flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:38:01 -07:00
Alex Forencich
f58d922e8f fpga/mqnic: Use correct clock frequencies in 25G testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 20:20:01 -07:00
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
6f197c7cb4 Add PHY instances to Ethernet pblocks 2022-03-24 21:30:55 -07:00
Alex Forencich
056f78716a Add pipeline registers 2022-03-17 15:39:44 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
67bd69a8d7 Unified 10G/25G design for AU50 2022-03-14 21:36:30 -07:00
Alex Forencich
8168469ec8 Update config.tcl 2022-03-14 14:45:38 -07:00
Alex Forencich
d9e79c9923 Rename cores to match transceiver type 2022-03-03 22:41:34 -08:00
Alex Forencich
16111eb7a8 Update AU50 to use new wrapper 2022-03-03 20:15:06 -08:00
Alex Forencich
2909d205de Remove unused files 2022-02-16 17:40:28 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
c98258bf05 Fix parametrization 2022-02-13 23:19:09 -08:00
Alex Forencich
627ac359d5 Add layer 2 ingress/egress modules 2022-02-13 23:09:41 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
8548e8570f Update vivado.mk 2021-12-20 22:03:06 -08:00
Alex Forencich
7a43618e3c Use start_soon instead of fork 2021-12-10 20:43:21 -08:00
Alex Forencich
bc8a8cdc58 Update 100G designs to use correct clock for PTP RX timestamps 2021-11-19 01:54:58 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
af3b6312a9 Add PTP_USE_SAMPLE_CLOCK parameter to testbenches 2021-11-18 21:12:06 -08:00
Alex Forencich
5bf9de656c Update testbenches 2021-11-17 18:08:40 -08:00
Alex Forencich
38c85a6bcd Set subsystem ID based on board, remove unnecessary configuration settings 2021-11-02 15:32:55 -07:00
Alex Forencich
01871e46cb Rework GT instances in Alveo U50 10G design 2021-10-21 19:57:17 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
982edfeda7 Update file lists 2021-10-20 19:37:37 -07:00
Alex Forencich
39fbc194fd Update makefiles 2021-09-20 18:22:47 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00