FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
2,630 Commits 1 Branch 0 Tags
Commit Graph

71 Commits

Author SHA1 Message Date
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
eb530475fb More expressive flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:38:01 -07:00
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
a373753d6e Update VCU108 to use new wrapper 2022-03-03 22:23:43 -08:00
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
b7bc240aa6 Add JTAG and GPIO passthroughs to application section 2022-01-27 23:06:05 -08:00
Alex Forencich
aab30c8cd0 Add transceiver quad wrappers 2022-01-16 18:28:22 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
886111c9e6 Update 10G designs for PTP separate RX clock 2021-11-19 01:52:23 -08:00
Alex Forencich
8f15664092 Rework GT instances in VCU118 design 2021-10-21 18:50:55 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
bfea350194 Update VCU108 design 2021-09-12 23:17:50 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
f71d28c6d8 Normalize RAM size and max frame size 2021-08-20 21:18:44 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
38f766646b Connect flow control signals to pcie_us_if 2021-08-12 00:05:43 -07:00
Alex Forencich
6517d43ee7 Add missing connection 2021-08-11 23:52:44 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
0b65a1271a Use new PCIe DMA modules 2021-08-04 01:20:57 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
1aeeb0bbe2 Update designs for PTP CDC and Ethernet MAC module changes 2021-03-30 16:41:31 -07:00
Alex Forencich
d0b19efce5 Reconcile PCIe changes 2021-03-01 00:25:15 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
151ed7e179 Add extra reset registers 2021-01-31 11:10:03 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
53f4275ea2 Add output registers for I2C interface to improve timing 2020-10-13 23:52:52 -07:00
Alex Forencich
d6810db7f5 Add extra output register for flash interface to improve routability and timing 2020-10-08 19:22:28 -07:00
Alex Forencich
10357d97d4 Add BPI flash access and IPROG for VCU108 2020-10-02 20:44:47 -07:00
Alex Forencich
96f015d905 Update LED connections 2020-09-29 00:38:04 -07:00
Alex Forencich
70b7082fb6 Implement new control registers 2020-09-19 17:25:58 -07:00
Alex Forencich
c8f5bb235c Remove extraneous clock connections 2020-08-19 18:33:41 -07:00
Alex Forencich
f99736d4f5 Convert to TCL IP 2020-07-11 20:07:13 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
9e3e80661c Use common sync_reset module 2020-03-27 23:53:05 -07:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00