Alex Forencich
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e0d92172d3
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Separate PTP TX clock input
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:24:41 -07:00 |
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Alex Forencich
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33b798540e
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Change hex format in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-09 14:20:48 -07:00 |
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Alex Forencich
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729c3a0458
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Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-08 22:07:18 -07:00 |
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Alex Forencich
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a5d7833bd9
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Update testbenches for new version of cocotbext-pcie
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2022-06-05 00:24:42 -07:00 |
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Alex Forencich
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21b0f014a5
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Switch to MSI-X
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:58:29 -07:00 |
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Alex Forencich
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dd2853bf40
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Update testbenches for latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-30 13:10:39 -07:00 |
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Alex Forencich
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835f0d38f0
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Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-06 17:46:16 -07:00 |
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Alex Forencich
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18d5c325bf
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Fix CMAC RX PTP timestamps
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-05 23:21:11 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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f67c704b11
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Update placement constraints for hierarchy changes
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-02 13:16:20 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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53f3547ef5
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Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-29 14:32:57 -07:00 |
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Alex Forencich
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2bd8350276
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Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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7f8bbe30de
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Add application ID
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 13:15:45 -07:00 |
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Alex Forencich
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ba70498518
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fpga: Add DMA immediate connections and parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-20 15:00:58 -07:00 |
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Alex Forencich
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1ffbd2d8d3
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mqnic/fpga/XUPP3R: Add 10G, 25G, and 100G mqnic designs for BittWare XUP-P3R board
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-16 12:33:50 -07:00 |
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