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Author SHA1 Message Date
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
2baae23f94 Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:55 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
969169c315 Clean up module instantiation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:19:30 -07:00
Alex Forencich
f29f72bab9 Change interval 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:55 -07:00
Alex Forencich
f19d993d8b Rework build_images settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:42 -07:00
Alex Forencich
6b0df7f33f Rework RX request generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:43:39 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
3c1865a81e merged changes in pcie 2022-07-06 23:19:43 -07:00
Alex Forencich
edd1d546d5 Fix 256-bit RC interface framing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-06 23:14:19 -07:00
Alex Forencich
ce233c6c2b Use latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 13:17:55 -07:00
Alex Forencich
a17c33e3c6 Update example designs to enable TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 01:31:15 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
103d7abdd9 Rework framing signal generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-03 22:38:16 -07:00
Alex Forencich
a44f9852c2 Update Stratix 10 H-tile/L-tile shim to support segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:48:46 -07:00
Alex Forencich
26c7128b7e Tie off unused port 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:42:03 -07:00
Alex Forencich
24dd0af398 Adjust MSI-X TLP port configuration for single segment, single DWORD operations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:41:51 -07:00
Alex Forencich
5658af86e0 Add PCIe TLP FIFO mux module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:41:27 -07:00
Alex Forencich
cc1278f9d9 Update PCIe TLP mux to handle multiple segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:40:35 -07:00
Alex Forencich
23705eb873 Update PCIe TLP demux to handle segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:39:38 -07:00
Alex Forencich
fc42368bd5 Add segmented PCIe TLP FIFO module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:35:57 -07:00
Alex Forencich
a5e81d7575 Ensure wide RAMs are marked for MLAB inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:28:44 -07:00
Alex Forencich
b044ac10ff Optimize offset_next computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:25:45 -07:00
Alex Forencich
93c2804b1b Add pipeline register after barrel shift 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:24:28 -07:00
Alex Forencich
8797aa481f Rework status FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 15:24:05 -07:00
Alex Forencich
87e155949c Add a simple block transfer measurement 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-19 22:52:16 -07:00
Alex Forencich
9b74e02408 Add jinja2 to tox.ini 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 01:36:12 -07:00
Alex Forencich
1ca13c3af2 Add TLP mux and demux tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 01:06:29 -07:00
Alex Forencich
2d48255ba3 Add mux and demux wrapper generators 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 01:06:01 -07:00
Alex Forencich
056500dbf4 Avoid zero-width replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:52:29 -07:00
Alex Forencich
72e8bad417 Normalize interfaces 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:51:37 -07:00
Alex Forencich
4818f2595c Fix initial reg value 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-13 00:27:44 -07:00
Alex Forencich
d1e21cb78b Add shim stress tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-12 23:30:27 -07:00
Alex Forencich
a096519fd8 Fix backpressure feedback bug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-12 23:27:38 -07:00
Alex Forencich
630648d5b0 Fix default parameter values 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 22:58:26 -07:00
Alex Forencich
58d705b924 Add channel testbenches for S10 shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:50:38 -07:00
Alex Forencich
07970ae41d Add channel testbenches for UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:13:21 -07:00
Alex Forencich
33e21a6f9b Remove extraneous parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:09:06 -07:00
Alex Forencich
48daa02897 Update example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-07 14:35:39 -07:00
Alex Forencich
27f749d5a5 Add strobe outputs to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-07 14:23:24 -07:00
Alex Forencich
52e7af8a5d Add combined TX/RX bus with all signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 19:09:15 -07:00
Alex Forencich
df32016724 Add sequence number ports to TLP mux and demux modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 17:34:12 -07:00
Alex Forencich
c95e8f70f2 Update PCIe TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:31:10 -07:00
Alex Forencich
5595953d5a merged changes in pcie 2022-06-05 14:30:42 -07:00
Alex Forencich
aadcd53c87 Update AXI DMA IF tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:29:16 -07:00
Alex Forencich
7d92722fe8 Clean up testbench parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:25:28 -07:00
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
ee59fc10e0 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:26:27 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00