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Author SHA1 Message Date
Alex Forencich
b1c6bdbd88 merged changes in pcie 2021-06-27 14:05:12 -07:00
Alex Forencich
cd9f6a9329 Use defines instead of magic numbers 2021-06-27 14:04:43 -07:00
Alex Forencich
5d153635f4 Set algorithm for pytest-split 2021-06-27 14:03:59 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
36a361d7c3 Update test durations 2021-06-18 18:42:44 -07:00
Alex Forencich
6b0076debc Work around pytest-split bug 2021-06-18 18:41:26 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
a79027fdd1 Remove DEV_BAR_CNT define 2021-06-16 21:36:34 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
4d89e70b92 merged changes in axi 2021-06-02 17:57:51 -07:00
Alex Forencich
bea7ff909f merged changes in pcie 2021-06-02 17:57:45 -07:00
Alex Forencich
7558949e12 merged changes in eth 2021-06-02 17:57:39 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
846183bc8b merged changes in axis 2021-06-02 17:06:26 -07:00
Alex Forencich
31378c4e85 Remove string parameters 2021-06-02 17:05:29 -07:00
Alex Forencich
5063aeadcd Remove string parameters 2021-06-02 17:04:53 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
e4e05ed1e3 Update readme 2021-06-01 16:29:52 -07:00
Alex Forencich
51caad0810 Extract port counts 2021-06-01 13:22:48 -07:00
Alex Forencich
a852697707 Fix instance names in wrappers 2021-06-01 13:18:11 -07:00
Alex Forencich
0512664ae0 merged changes in axis 2021-06-01 13:03:13 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
e32f65f563 Update test durations 2021-05-30 12:39:49 -07:00
Alex Forencich
5d9c982cd4 Add switch testbenches 2021-05-30 12:33:29 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00
Alex Forencich
9417d5f749 Use cocotb.top 2021-05-30 12:32:02 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
c1bfa8cc41 Add tuser assert tests 2021-05-25 00:55:59 -07:00
Alex Forencich
a7905ed681 Add stress tests 2021-05-25 00:31:20 -07:00
Alex Forencich
a7ebfdcebb Add arbitration test 2021-05-25 00:13:32 -07:00
Alex Forencich
15cb21dbd1 Reorganize timing constraints 2021-05-20 15:24:01 -07:00
Alex Forencich
5ebc741ffe merged changes in axi 2021-05-20 15:17:25 -07:00
Alex Forencich
955fdbf391 merged changes in pcie 2021-05-20 15:17:19 -07:00
Alex Forencich
9c4012f58d Reorganize timing constraints 2021-05-20 15:15:51 -07:00
Alex Forencich
892aa58004 merged changes in eth 2021-05-20 15:13:16 -07:00
Alex Forencich
b09e01ba48 Update S10MX SDC 2021-05-19 21:57:48 -07:00
Alex Forencich
9df253aa59 Update readme 2021-05-19 21:57:33 -07:00
Alex Forencich
cee82cb695 Add Stratix 10 DX 10G example design 2021-05-19 21:00:54 -07:00
Alex Forencich
13c1bbe79a Update S10MX QSF 2021-05-19 16:48:58 -07:00
Alex Forencich
1a3c68812f Update readme 2021-05-18 22:33:01 -07:00
Alex Forencich
0d21ea80ea Update readme 2021-05-18 22:16:50 -07:00
Alex Forencich
0c493c4ba1 Update readme 2021-05-18 22:11:32 -07:00
Alex Forencich
28686fb115 Update readme 2021-05-18 22:05:44 -07:00
Alex Forencich
20c7967715 Update readme 2021-05-18 19:16:48 -07:00
Alex Forencich
bf6fddd1db Add Stratix 10 MX 10G example design 2021-05-18 19:16:30 -07:00
Alex Forencich
40265a3e1c Add timing constraints for Quartus Prime Pro 2021-05-18 18:30:33 -07:00