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Author SHA1 Message Date
Alex Forencich
4b261150d2 Update axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:57:02 -07:00
Alex Forencich
0b815522b0 Sync example design testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:55 -07:00
Alex Forencich
e4b1df0ddb Fix immediate enable register implementation in example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 00:43:21 -07:00
Alex Forencich
ffc0a70c40 Update scripts to use setpci built-in bit masking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-19 23:18:50 -07:00
Alex Forencich
984aefe508 Fix tag indexing 2022-04-06 13:24:05 -07:00
Alex Forencich
89db2a29b7 When EXTEND_RAM_SEL is not set, do not modify ram_sel 2022-04-06 13:23:46 -07:00
Alex Forencich
32b4f2cb1f Improve block operation tests 2022-04-04 15:21:25 -07:00
Alex Forencich
43719a9f73 Cleanup 2022-04-04 15:05:46 -07:00
Alex Forencich
e7a83364d0 Update testbenches 2022-04-04 15:05:21 -07:00
Alex Forencich
389911e126 Update example design to test immediate write 2022-04-04 15:04:57 -07:00
Alex Forencich
a5dcb3d27c Add support for writing immediate data to DMA IF modules 2022-04-04 12:40:42 -07:00
Alex Forencich
34fe24287d Simplify logic 2022-04-01 01:42:25 -07:00
Alex Forencich
7fcec10961 Add internal RAM_DATA_WIDTH parameter 2022-04-01 01:11:30 -07:00
Alex Forencich
1f46987ed8 Fix typo in Stratix 10 shim 2022-03-31 23:19:50 -07:00
Alex Forencich
4bbd187567 Add statistics outputs to AXI DMA IF modules 2022-03-31 17:56:05 -07:00
Alex Forencich
dd7cc63d55 Correct reporting of request length statistics for zero-length operations in PCIe DMA IF modules 2022-03-31 17:04:03 -07:00
Alex Forencich
2aeb820d35 Add operation table size assertion in AXI DMA IF modules 2022-03-31 16:42:46 -07:00
Alex Forencich
ac5f942128 Support error reporting in AXI DMA interface modules 2022-03-31 01:48:36 -07:00
Alex Forencich
0b9c7671fb Minor refactor of zero-length handling logic 2022-03-31 00:05:55 -07:00
Alex Forencich
7cae50fa10 Support zero-length operations in AXI DMA interface modules 2022-03-30 23:40:02 -07:00
Alex Forencich
3f967c673f Read zero length flag on all paths 2022-03-30 23:39:34 -07:00
Alex Forencich
32fe17ad91 Return 0 for unmatched registers 2022-03-25 23:56:42 -07:00
Alex Forencich
c62df81292 Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH 2022-02-15 00:39:46 -08:00
Alex Forencich
a65b256b85 Update default SEG_ADDR_WIDTH parameter value for DMA RAM 2022-02-14 22:28:50 -08:00
Alex Forencich
c47332462d Implement USE_AXI_ID for dma_if_axi_rd 2022-02-01 16:29:56 -08:00
Alex Forencich
27f90934fe Refactor to use existing variable 2022-02-01 16:27:13 -08:00
Alex Forencich
a0a7732801 Add missing resets 2022-02-01 16:26:12 -08:00
Alex Forencich
2f6ad1e28d Implement USE_AXI_ID for dma_if_axi_wr 2022-02-01 00:43:21 -08:00
Alex Forencich
d9c4b173e9 Update parameters 2022-02-01 00:23:52 -08:00
Alex Forencich
74e4322d43 Fix bug in example design core logic 2022-01-17 21:45:49 -08:00
Alex Forencich
625f3c9823 Lock package versions 2021-12-27 16:54:25 -08:00
Alex Forencich
7ab512bd32 Specify min tox and venv versions 2021-12-27 16:53:42 -08:00
Alex Forencich
4ce150e588 Use available python 3 2021-12-27 13:52:23 -08:00
Alex Forencich
25f6dcb383 Fix alignment 2021-12-16 00:30:07 -08:00
Andreas Braun
01b97322c1 Fix reg to wire declaration 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2021-12-16 00:27:43 -08:00
Alex Forencich
bac4e4066f Use start_soon instead of fork 2021-12-10 17:44:37 -08:00
Ulrich Langenbach
5e708ca4c7 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 
the same as fixed in verilog-pcie 3a124837115e51e2273ab7d1c61d80ee01f891c1
in dma_ram_demux_rd.v adapted to module dma_ram_demux_wr.v
 2021-12-10 17:39:49 +01:00
Alex Forencich
17d7353523 Indexing updates 2021-12-02 16:59:16 -08:00
Alex Forencich
3a12483711 Fix multi-driven net issue when S_RAM_SEL_WIDTH = 0 2021-12-02 16:50:26 -08:00
Alex Forencich
a2e2919add Update readme 2021-11-18 16:34:43 -08:00
Alex Forencich
d1210d02a3 Add example design for ZCU106 2021-11-18 16:33:39 -08:00
Alex Forencich
0830ca6a7a Add example design for VCU1525 2021-11-18 16:32:38 -08:00
Alex Forencich
fb4b32fba0 Add example design for VCU118 2021-11-18 16:31:55 -08:00
Alex Forencich
cef69d1e1f Add example design for VCU108 2021-11-18 16:31:18 -08:00
Alex Forencich
6740ddafaf Add example design for ExaNIC X25 2021-11-18 16:29:52 -08:00
Alex Forencich
0cbe4897da Add example design for Alveo U50 2021-11-18 16:28:39 -08:00
Alex Forencich
068ea6edc2 Add example design for Alveo U280 2021-11-18 16:27:48 -08:00
Alex Forencich
12fea955d2 Add example design for Alveo U250 2021-11-18 16:26:43 -08:00
Alex Forencich
6e5f9f33f2 Add example design for Alveo U200 2021-11-18 16:25:59 -08:00
Alex Forencich
057edebc36 Add example design for ADM-PCIE-9V3 2021-11-18 16:21:28 -08:00