376 Commits

Author	SHA1	Message	Date
Alex Forencich	b630fdaeb0	Fix QSFP mapping comments	2021-09-01 02:01:14 -07:00
Alex Forencich	9295184e19	Fix signal width parametrization	2021-09-01 01:59:42 -07:00
Alex Forencich	fc835e0ab6	Use TX PTP CDC for both RX and TX due to synchronous clocking	2021-08-31 23:38:24 -07:00
Alex Forencich	82d0770daf	Remove unused constraints file	2021-08-31 23:33:00 -07:00
Alex Forencich	c3d498101b	Clarify widths	2021-08-31 23:32:42 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	1fc991fc05	Convert fb2CG designs to use common core modules	2021-08-31 21:33:49 -07:00
Alex Forencich	915a915d6e	Enable PCIe flow control in core tests	2021-08-31 20:38:08 -07:00
Alex Forencich	bd3fa6abfd	Update vivado.mk	2021-08-31 20:03:33 -07:00
Alex Forencich	a5519cd607	Default to US+ configuration	2021-08-31 18:57:32 -07:00
Alex Forencich	bdbdc11841	Initial commit of core logic	2021-08-31 18:42:19 -07:00
Alex Forencich	9731ea5188	Add new PTP subsystem	2021-08-31 01:39:19 -07:00
Alex Forencich	cef2602efe	Reorganize address space to place port registers in interface register space	2021-08-30 01:29:25 -07:00
Alex Forencich	d46cb16dbf	Add scheduler block	2021-08-30 01:28:55 -07:00
Alex Forencich	d8615468e9	merged changes in eth	2021-08-30 01:28:13 -07:00
Alex Forencich	cee999a201	merged changes in axi	2021-08-30 01:28:08 -07:00
Alex Forencich	454d237ab2	Rename parameter	2021-08-30 01:27:53 -07:00
Alex Forencich	f71d28c6d8	Normalize RAM size and max frame size	2021-08-20 21:18:44 -07:00
Alex Forencich	4ceefa376a	Normalize FIFO size to 32K	2021-08-20 21:17:41 -07:00
Alex Forencich	34150323df	Remove obsolete packet table size parameters	2021-08-20 18:15:06 -07:00
Alex Forencich	43364943e1	merged changes in pcie	2021-08-20 16:10:32 -07:00
Alex Forencich	84e19ca305	Update file lists	2021-08-16 18:12:19 -07:00
Alex Forencich	fb241ae992	merged changes in pcie	2021-08-16 18:06:46 -07:00
Alex Forencich	38f766646b	Connect flow control signals to pcie_us_if	2021-08-12 00:05:43 -07:00
Alex Forencich	6517d43ee7	Add missing connection	2021-08-11 23:52:44 -07:00
Alex Forencich	09c90e321b	merged changes in pcie	2021-08-11 23:38:41 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	07292b7dda	merged changes in axi	2021-08-11 01:28:07 -07:00
Alex Forencich	3e489fde27	Fix instance name	2021-08-04 12:37:13 -07:00
Alex Forencich	49aa27d1c5	Add placement constraints for AU50	2021-08-04 01:23:22 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	038772b175	merged changes in pcie	2021-08-04 01:07:22 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	6e178377c3	merged changes in pcie	2021-08-02 22:46:16 -07:00
Alex Forencich	b0ed724d70	merged changes in pcie	2021-07-25 02:24:33 -07:00
Alex Forencich	4ed99c6f87	Remove CMS IP version number	2021-07-03 00:09:10 -07:00
Alex Forencich	c926fd2ca1	Remove extraneous imports	2021-06-28 22:35:22 -07:00
minseongg	9af504a6c0	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	8db2faddc6	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	b1c6bdbd88	merged changes in pcie	2021-06-27 14:05:12 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	4d89e70b92	merged changes in axi	2021-06-02 17:57:51 -07:00
Alex Forencich	bea7ff909f	merged changes in pcie	2021-06-02 17:57:45 -07:00
Alex Forencich	7558949e12	merged changes in eth	2021-06-02 17:57:39 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	5ebc741ffe	merged changes in axi	2021-05-20 15:17:25 -07:00
Alex Forencich	955fdbf391	merged changes in pcie	2021-05-20 15:17:19 -07:00
Alex Forencich	892aa58004	merged changes in eth	2021-05-20 15:13:16 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00