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Author SHA1 Message Date
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00
Alex Forencich
811b9daa63 Add missing connection 2021-08-11 19:18:50 -07:00
Alex Forencich
8e19f6edb8 Tie off outputs if configuration read functionality is disabled 2021-08-11 19:17:55 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
07292b7dda merged changes in axi 2021-08-11 01:28:07 -07:00
Alex Forencich
fe283eee02 Update readme 2021-08-11 01:25:42 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00
Alex Forencich
39dc8662b6 Remove duplicate code 2021-08-11 01:16:02 -07:00
Alex Forencich
81673727a4 Fix broadcast address check 2021-08-08 13:25:39 -07:00
Alex Forencich
c47f3f5280 AT is reserved in completions 2021-08-06 01:49:47 -07:00
Alex Forencich
1c424a8a51 Read locked is UR for PCIe endpoints 2021-08-06 01:39:11 -07:00
Alex Forencich
f8f95a214b Set completer ID in testbench 2021-08-04 17:08:25 -07:00
Alex Forencich
3e489fde27 Fix instance name 2021-08-04 12:37:13 -07:00
Alex Forencich
49aa27d1c5 Add placement constraints for AU50 2021-08-04 01:23:22 -07:00
Alex Forencich
0b65a1271a Use new PCIe DMA modules 2021-08-04 01:20:57 -07:00
Alex Forencich
038772b175 merged changes in pcie 2021-08-04 01:07:22 -07:00
Alex Forencich
d3690a12ab Update readme 2021-08-04 01:04:31 -07:00
Alex Forencich
12f90eac5b Update test durations 2021-08-04 01:04:20 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00
Alex Forencich
623cc1ae8d Add generic PCIe interface model 2021-08-03 22:33:23 -07:00
Alex Forencich
bf3143a79f Fix test name 2021-08-03 01:54:00 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
6e178377c3 merged changes in pcie 2021-08-02 22:46:16 -07:00
Alex Forencich
e4508b242f Update example designs 2021-08-02 18:36:25 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
db826e489b Set algorithm for pytest-split 2021-08-01 01:19:07 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:43:33 -07:00
Alex Forencich
b0ed724d70 merged changes in pcie 2021-07-25 02:24:33 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
59c026b1b8 Fix parameters 2021-07-24 02:02:30 -07:00
Alex Forencich
3e03b20bc7 Properly handle zero-length PCIe read and write operations 2021-07-24 01:13:25 -07:00
Alex Forencich
29313d5e02 Add HTG-9200 10G example design 2021-07-08 11:58:04 -07:00
Alex Forencich
4ed99c6f87 Remove CMS IP version number 2021-07-03 00:09:10 -07:00
Alex Forencich
c926fd2ca1 Remove extraneous imports 2021-06-28 22:35:22 -07:00
minseongg
9af504a6c0 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
8db2faddc6 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
dc5c8232f9 Add cmac_pad testbench 2021-06-28 22:33:57 -07:00
Alex Forencich
cf832f581c Set algorithm for pytest-split 2021-06-28 01:34:34 -07:00
Alex Forencich
b1c6bdbd88 merged changes in pcie 2021-06-27 14:05:12 -07:00
Alex Forencich
cd9f6a9329 Use defines instead of magic numbers 2021-06-27 14:04:43 -07:00
Alex Forencich
5d153635f4 Set algorithm for pytest-split 2021-06-27 14:03:59 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00