Alex Forencich
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519330fd32
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fpga: Move led_sreg_driver into common
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-27 14:12:42 -07:00 |
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Alex Forencich
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04ede2e535
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fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-06 14:34:22 -07:00 |
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Alex Forencich
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5b859b08a0
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Use false path constraints for status signals that change infrequently
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-17 14:25:30 -08:00 |
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Alex Forencich
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bbdb44ce01
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fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-08 18:50:30 -08:00 |
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Alex Forencich
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bf7cf3fef9
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Add CMAC wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-09 20:58:30 -08:00 |
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Alex Forencich
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d3942da875
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fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-15 19:45:02 -07:00 |
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Alex Forencich
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ed2d34153d
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Use PHY rx_status signal for link status detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-17 00:46:05 -07:00 |
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Alex Forencich
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835f0d38f0
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Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-06 17:46:16 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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e91de95955
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Fix rb_drp timing constraint for write enable signal
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2022-03-02 17:31:17 -08:00 |
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Alex Forencich
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90d28ec9a2
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Add common 10G PHY + GTH/GTY transceiver wrapper module
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2022-03-02 17:28:40 -08:00 |
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Alex Forencich
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614b391c48
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Add DRP register block
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2022-02-21 23:20:54 -08:00 |
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Alex Forencich
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15cb21dbd1
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Reorganize timing constraints
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2021-05-20 15:24:01 -07:00 |
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