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Author SHA1 Message Date
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-18 12:07:11 -07:00
Alex Forencich
fc5964ab90 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 20:00:01 -07:00
Alex Forencich
ce8dcdafe8 Pipeline arbitration delay in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:26 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
96716b0556 Lock package versions 2021-12-27 16:54:24 -08:00
Alex Forencich
fef6b167bc Specify min tox and venv versions 2021-12-27 16:53:40 -08:00
Alex Forencich
61fbb2d76f Use available python 3 2021-12-27 16:51:58 -08:00
Alex Forencich
4df34f1344 Use start_soon instead of fork 2021-12-10 18:16:38 -08:00
Alex Forencich
2a89fb9332 Testbench parameter cleanup 2021-11-29 01:01:45 -08:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
f40e68350c Remove deprecated assigments 2021-11-15 14:39:47 -08:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
10e24cc5b1 Fix timing constraints 2021-10-13 18:07:45 -07:00
Alex Forencich
4f1eabab17 Split async FIFO resets 2021-10-13 14:05:13 -07:00
Alex Forencich
e0da1819c4 More tests for pipeline FIFO 2021-09-28 01:18:17 -07:00
Alex Forencich
0b5fc5b0e0 Fix off by one error 2021-09-28 01:17:57 -07:00
Alex Forencich
e48901a588 Reorganize test lists 2021-09-28 01:17:28 -07:00
Alex Forencich
d549267e17 Test async FIFO with different clock periods 2021-09-28 00:29:54 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
763cc1669f Update test durations 2021-06-03 13:52:41 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
e32f65f563 Update test durations 2021-05-30 12:39:49 -07:00
Alex Forencich
5d9c982cd4 Add switch testbenches 2021-05-30 12:33:29 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00
Alex Forencich
9417d5f749 Use cocotb.top 2021-05-30 12:32:02 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
c1bfa8cc41 Add tuser assert tests 2021-05-25 00:55:59 -07:00
Alex Forencich
a7905ed681 Add stress tests 2021-05-25 00:31:20 -07:00
Alex Forencich
a7ebfdcebb Add arbitration test 2021-05-25 00:13:32 -07:00