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19 Commits

Author SHA1 Message Date
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Ulrich Langenbach
984a58684c fix partial initialisation of memory 
the fixed issue has been introduced in 0560f98e799d741d62522e61bf23321fc3f2880b
 2022-03-24 15:50:25 -07:00
Ulrich Langenbach
0560f98e79 support more than 4k queues (workaround quartus loop iteration limit) 2021-12-16 12:09:39 -08:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
5d760851ac Limit queue manager pipelines to a single AXI lite operation 2021-09-05 12:46:56 -07:00
Alex Forencich
d0cf549057 Add log desc block size field to queue manager 2020-04-20 20:45:10 -07:00
Alex Forencich
50af74aa88 Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH 2020-04-20 18:43:26 -07:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00
Alex Forencich
bee056e7d3 Fix pipelining bug 2019-09-13 13:48:48 -07:00
Alex Forencich
6d78315f81 Add queue index to queue operation response 2019-09-01 08:12:06 -07:00
Alex Forencich
e548bd0238 Initialize RAMs 2019-08-20 01:06:29 -07:00
Alex Forencich
451acd3af5 Parametrize queue RAM width 2019-08-11 15:15:55 -07:00
Alex Forencich
1e06d7cca7 Clean up pipeline parameters 2019-08-11 09:55:10 -07:00
Alex Forencich
46fe4bbd97 Remove extraneous code 2019-08-11 00:34:50 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00