Alex Forencich
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9963674c61
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Add flow control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-09 19:01:36 -07:00 |
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Alex Forencich
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2e387d3630
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fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-05 23:44:12 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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c5003d0c6d
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fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-03 15:35:16 -08:00 |
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Alex Forencich
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61caf147f7
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Use CMAC wrapper in 100G mqnic design for XUP-P3R
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-10 18:26:10 -08:00 |
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Alex Forencich
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5e52a52f5e
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fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 19:00:49 -07:00 |
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Alex Forencich
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729c3a0458
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Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-08 22:07:18 -07:00 |
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Alex Forencich
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21b0f014a5
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Switch to MSI-X
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:58:29 -07:00 |
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Alex Forencich
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1ffbd2d8d3
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mqnic/fpga/XUPP3R: Add 10G, 25G, and 100G mqnic designs for BittWare XUP-P3R board
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-16 12:33:50 -07:00 |
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