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Author SHA1 Message Date
Alex Forencich
d5df47d8b0 Use quad wrappers in ZCU106 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:04 -07:00
Alex Forencich
4618edcd8e Use quad wrappers in VCU108 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:15:29 -07:00
Alex Forencich
72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:09:00 -07:00
Alex Forencich
66987c8f62 Use quad wrappers in AU280 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:08:32 -07:00
Alex Forencich
22f327b35f Use quad wrappers in AU250 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:07:30 -07:00
Alex Forencich
65361d157b Use quad wrappers in AU200 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:06:28 -07:00
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
1e88ed3d2e Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:12:59 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
88166c1153 modules/mqnic: Drop short frames 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-23 17:50:20 -07:00
Alex Forencich
6e67bd652e fpga/mqnic/fb4CGg3: Add DRAM support on fb4CGg3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 23:53:13 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
f1884b98bf Add unified 10G/25G mqnic design for BittWare XUSP3S board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 12:55:11 -07:00
Alex Forencich
24c758dbde fpga/mqnic/XUPP3R: Update XUP-P3R pins 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 12:53:43 -07:00
Alex Forencich
99645f894e Use shallow async FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-17 02:00:12 -07:00
Alex Forencich
053884506c merged changes in eth 2023-08-16 16:24:05 -07:00
Alex Forencich
f92a94d278 merged changes in axis 2023-08-16 16:19:04 -07:00
Alex Forencich
7823b916bf Implement MARK_WHEN_FULL option in FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-16 12:50:12 -07:00
Alex Forencich
6020d09214 Reorganize FIFO write logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 18:55:02 -07:00
Alex Forencich
c3cd676c5d Test DROP_WHEN_FULL parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:57 -07:00
Alex Forencich
c4f298de6f Add overflow test, previous test is actually an oversize frame test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:30 -07:00
Alex Forencich
330d6f41fc Send more data in stress tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:14 -07:00
Alex Forencich
3a665f0ded Compute DEPTH based on FIFO data width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:35 -07:00
Alex Forencich
7febd080c9 Use FIFO depth in overflow test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:22 -07:00
Alex Forencich
ac2c0fdac8 Read configuration directly from DUT 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:30 -07:00
Alex Forencich
62c2148c8f Add pause functionality to FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:16 -07:00
Alex Forencich
e308c9559a Rewrite width converter to reduce resource consumption 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:54 -07:00
Alex Forencich
31bac4e21f Reorganize FIFO adapter wrappers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:33 -07:00
Alex Forencich
a052b0eb32 Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-28 18:38:12 -07:00
Alex Forencich
d6fc68947b Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 20:25:08 -07:00
Alex Forencich
6b00ff29c8 merged changes in axis 2023-07-27 01:45:14 -07:00
Alex Forencich
1628a1a043 Reorganize pipeline FIFO to facilitate placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 01:43:36 -07:00
Alex Forencich
10da93fec4 Add depth status outputs to FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 20:02:43 -07:00
Alex Forencich
2be72bb758 Refactor pointer handling in FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 18:47:43 -07:00
Alex Forencich
9cb38fa2a0 Remove extraneous parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 16:48:28 -07:00
Alex Forencich
a443e8862c Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:59:19 -07:00
Alex Forencich
4f7c0ebe2a merged changes in axis 2023-07-26 14:53:57 -07:00
Alex Forencich
9bc052de8b Another update to async FIFO timing constraints to deal with OOC clock constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 14:53:01 -07:00
Alex Forencich
6a6d1f0ac0 fpga/mqnic: Clean up some aditional file headers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-26 00:51:23 -07:00
Alex Forencich
02ce168c63 Improve PTP-related tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 01:01:54 -07:00
Alex Forencich
fa173f93e5 Avoid testbench reset during alignment test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-24 00:57:43 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00
Alex Forencich
78284572ef Remove XDC constraints that do not apply to Artix 7 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 18:35:22 -07:00
Alex Forencich
ba5a883433 Add pause/PFC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 16:31:33 -07:00