17 Commits

Author	SHA1	Message	Date
Alex Forencich	ba70498518	fpga: Add DMA immediate connections and parameters ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-04-20 15:00:58 -07:00
Alex Forencich	f687aba432	fpga/mqnic: Update designs to use port mapping modules ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-04-13 01:37:10 -07:00
Alex Forencich	f082196b4a	Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level	2022-03-29 23:15:06 -07:00
Alex Forencich	cbd9d0dfc6	Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports	2022-03-28 17:23:27 -07:00
Alex Forencich	09128df360	Add SCHED_PER_IF parameter to split scheduler count from port count	2022-03-28 15:20:33 -07:00
Alex Forencich	dfae34ed25	Pass through PTP pipelining settings	2022-03-28 00:50:29 -07:00
Alex Forencich	2909d205de	Remove unused files	2022-02-16 17:40:28 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	886111c9e6	Update 10G designs for PTP separate RX clock	2021-11-19 01:52:23 -08:00
Alex Forencich	af3b6312a9	Add PTP_USE_SAMPLE_CLOCK parameter to testbenches	2021-11-18 21:12:06 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	76e18d2af8	Add 10G mqnic design for Stratix 10 MX dev kit	2021-11-07 13:59:05 -08:00