Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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2bd8350276
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Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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7f8bbe30de
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Add application ID
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 13:15:45 -07:00 |
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Alex Forencich
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eb530475fb
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More expressive flash format register
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-15 18:38:01 -07:00 |
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Alex Forencich
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1797fdecec
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docs: Fix table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-07 22:42:47 -07:00 |
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Alex Forencich
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cbd9d0dfc6
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Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
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2022-03-28 17:23:27 -07:00 |
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Alex Forencich
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1e601cff56
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Initial commit of sphinx documentation
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2022-03-13 23:32:01 -07:00 |
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