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7 Commits

Author SHA1 Message Date
Alex Forencich
d3eb4ee473 Update documentation on operations on the RX and TX paths through the application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-01 17:22:16 -08:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
4cdb57bfe1 Update module documentation 2022-05-23 21:23:13 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
4310c3e0e7 Pass SCHED_PER_IF and PTP_PORT_CDC_PIPELINE parameters through to application block 2022-03-28 21:57:53 -07:00
Alex Forencich
1e601cff56 Initial commit of sphinx documentation 2022-03-13 23:32:01 -07:00