1424 Commits

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Author	SHA1	Message	Date
Alex Forencich	bb19674dac	merged changes in pcie	2020-08-17 18:34:37 -07:00
Alex Forencich	44dd74eb0d	merged changes in eth	2020-08-17 18:33:49 -07:00
Alex Forencich	6b9a6c87d5	merged changes in axi	2020-08-17 18:33:45 -07:00
Alex Forencich	62d696a1dc	merged changes in axis	2020-08-17 18:31:56 -07:00
Alex Forencich	d7f96eb104	Rewrite priority encoder to remove recusive construction	2020-08-17 18:30:40 -07:00
Alex Forencich	ae10935a93	Rewrite priority encoder to remove recusive construction	2020-08-17 18:29:05 -07:00
Alex Forencich	00e2756385	Rewrite priority encoder to remove recusive construction	2020-08-17 18:28:59 -07:00
Alex Forencich	c1f31e537e	Remove unnecessary wait state when output is ready	2020-08-17 00:13:02 -07:00
Alex Forencich	ba0b96ca34	Use logical operators	2020-08-17 00:11:52 -07:00
Alex Forencich	8b789c89ae	Reset count_reg in axi_fifo_rd	2020-08-17 00:09:06 -07:00
Alex Forencich	9b019aba29	Add board ID for ZCU106	2020-08-06 23:33:54 -07:00
Alex Forencich	788bfe1aa5	Update readme	2020-08-06 23:26:20 -07:00
Alex Forencich	e6b35f0567	Add PCIe mqnic design for ZCU106	2020-08-06 23:25:23 -07:00
Alex Forencich	d97e95b6c7	Update XDC	2020-08-06 22:06:40 -07:00
Alex Forencich	fed4c93b9c	Update XDC	2020-08-06 22:06:16 -07:00
Alex Forencich	0b3d4e7e75	merged changes in pcie	2020-08-06 21:35:00 -07:00
Alex Forencich	1e75c3cc70	Fix AXI stream DMA client bug causing dropped writes when widths are the same	2020-08-06 21:32:10 -07:00
Alex Forencich	0d4e9989c8	Fix asserts	2020-08-06 21:31:58 -07:00
Alex Forencich	e54eb685b3	Update makefiles	2020-08-06 18:43:47 -07:00
Alex Forencich	bf589968fb	merged changes in eth	2020-08-06 18:32:31 -07:00
Alex Forencich	0d7a2dba2f	merged changes in pcie	2020-08-06 18:32:27 -07:00
Alex Forencich	2e3f2c97b6	Update readme	2020-08-06 18:26:18 -07:00
Alex Forencich	df5368d153	Add ZCU106 example design	2020-08-06 18:26:07 -07:00
Alex Forencich	963f4f8555	Add ZCU106 AXI example design	2020-08-06 18:25:34 -07:00
Alex Forencich	b79ddf5ebd	Update makefiles	2020-08-06 18:22:30 -07:00
Alex Forencich	6aba3a741a	Update makefiles	2020-08-06 17:19:11 -07:00
Alex Forencich	fd908dd2aa	Clean up clock connections	2020-08-06 17:15:38 -07:00
Alex Forencich	907bb68a99	Use misc device properly	2020-07-31 00:47:43 -07:00
Alex Forencich	6edce8c984	Add BAR size check	2020-07-30 23:48:52 -07:00
Alex Forencich	ae57fc941c	Add missing error code	2020-07-30 23:48:26 -07:00
Alex Forencich	5a9117cf8b	Remove unused code	2020-07-30 23:32:16 -07:00
Alex Forencich	e60e3a993f	Add device object reference in mqnic_dev and clean up references to device object	2020-07-30 19:37:34 -07:00
Alex Forencich	e7bcb726b4	Full de-init on shutdown	2020-07-30 19:30:36 -07:00
Alex Forencich	77b9cace47	Update BAR configuration in testbenches	2020-07-28 19:01:53 -07:00
Alex Forencich	ffd04d2bb0	Cleanup	2020-07-28 19:00:33 -07:00
Alex Forencich	495178e1dc	Fix mask	2020-07-28 18:30:52 -07:00
Alex Forencich	e4566dc545	merged changes in pcie	2020-07-28 16:00:31 -07:00
Alex Forencich	8045992eb6	Remove extraneous code	2020-07-27 22:29:04 -07:00
Alex Forencich	1f523f0bb4	Remove unused reg	2020-07-26 21:39:10 -07:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	dc48d86b99	Improve BAR initialization	2020-07-24 22:54:55 -07:00
Alex Forencich	d449be8fc5	Convert to 64 bit BARs	2020-07-24 16:54:57 -07:00
Alex Forencich	65fd5ef947	Fix AU50 XDC file	2020-07-23 22:36:00 -07:00
Alex Forencich	cdc14769c3	Update readme	2020-07-17 01:45:25 -07:00
Alex Forencich	2a23be508a	Add 100G mqnic design for Alveo U50	2020-07-17 01:44:59 -07:00
Alex Forencich	deb895ff05	Add 10G mqnic design for Alveo U50	2020-07-17 01:44:28 -07:00
Alex Forencich	18f56fcb16	Remove extraneous signals	2020-07-17 00:57:47 -07:00
Alex Forencich	dbd6f0f07c	Update readme	2020-07-17 00:07:45 -07:00
Alex Forencich	f0e130aa48	Add AU50 10G example design	2020-07-17 00:06:32 -07:00
Alex Forencich	56dbcb8274	Add AU50 AXI example design	2020-07-17 00:04:13 -07:00