Alex Forencich
|
bc2757dde9
|
Cache clock edge events
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-31 16:22:05 -08:00 |
|
Alex Forencich
|
9c5c6e6edf
|
Rework parameter handling in example design makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-29 22:56:53 -08:00 |
|
Alex Forencich
|
5de1bc0df1
|
Rework parameter handling in testbench makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-29 22:31:21 -08:00 |
|
Alex Forencich
|
0c951a4e5a
|
Split some long-running tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-26 21:55:58 -08:00 |
|
Alex Forencich
|
73728d1994
|
Adjust testbench timeouts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-26 18:47:15 -08:00 |
|
Alex Forencich
|
28916a56cd
|
Update CI configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-01-26 16:41:36 -08:00 |
|
Alex Forencich
|
6bfaef78bd
|
Properly handle 4KB read requests in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 21:52:27 -07:00 |
|
Alex Forencich
|
633037d032
|
Fix direction of config signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 21:40:08 -07:00 |
|
Alex Forencich
|
5e396ceb87
|
Rename seg_rc_hdr to seg_rq_hdr
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 21:19:48 -07:00 |
|
Alex Forencich
|
62711295e0
|
Update pcie_if model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-27 15:28:07 -07:00 |
|
Alex Forencich
|
1e3dae4767
|
Update package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-07 19:41:50 -07:00 |
|
Alex Forencich
|
916faa0bdd
|
Add IRQ rate limit module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 12:02:26 -07:00 |
|
Alex Forencich
|
d038ba9853
|
Minor cleanup of MSI-X module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-03 17:19:21 -07:00 |
|
Alex Forencich
|
a1e53e5e46
|
Fix latch inference
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-03 01:20:39 -07:00 |
|
Alex Forencich
|
a2f07db39f
|
Remove redundant abort signal connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-14 14:55:01 -07:00 |
|
Alex Forencich
|
60dd672f6d
|
Move pause signal connection to improve timing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-14 14:54:27 -07:00 |
|
Alex Forencich
|
edf9b260ab
|
Rename module to match file name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-14 14:53:15 -07:00 |
|
Alex Forencich
|
d6d59a5675
|
Don't force DMA RAM into MLABs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-05 16:25:18 -07:00 |
|
Alex Forencich
|
91450fcab7
|
PCIe flow control is handled in shim; remove flow control from PCIe DMA interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-03 13:47:02 -07:00 |
|
Alex Forencich
|
3f3be1e14d
|
Implement flow control for P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-02 22:57:27 -07:00 |
|
Alex Forencich
|
53ee26f3ec
|
Use latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-01 13:25:51 -07:00 |
|
Alex Forencich
|
7f0bd00170
|
Implement flow control for Stratix 10 shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-01 13:19:01 -07:00 |
|
Alex Forencich
|
9c434687a8
|
Add flow control credit counter to TLP FIFO MUX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:35:07 -07:00 |
|
Alex Forencich
|
ad5a322ee1
|
Add PCIe flow control credit count module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:24:43 -07:00 |
|
Alex Forencich
|
1dfdd8b0e3
|
Timing optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:24:03 -07:00 |
|
Alex Forencich
|
b1b82a3f2b
|
Add pause inputs to TLP mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-29 17:16:05 -07:00 |
|
Alex Forencich
|
0d9b1d0fb0
|
Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-26 14:01:00 -07:00 |
|
Alex Forencich
|
a5fe40cd42
|
Fix JTAG index
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:34:26 -07:00 |
|
Alex Forencich
|
a53509de68
|
Add instance names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:34:04 -07:00 |
|
Alex Forencich
|
90c65dfed7
|
Fix PBA offsets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:33:38 -07:00 |
|
Alex Forencich
|
5fe904545c
|
Testbench cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 16:35:51 -07:00 |
|
Alex Forencich
|
fc90d7f44d
|
Strip version number
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:40:43 -07:00 |
|
Alex Forencich
|
05f51ed05c
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:32:33 -07:00 |
|
Alex Forencich
|
be6bb907c9
|
Register MSI-X control signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:32:19 -07:00 |
|
Alex Forencich
|
dbcd211ce1
|
Add example design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:59 -07:00 |
|
Alex Forencich
|
c5382f5e7f
|
Add example design for Stratix 10 DX dev kit
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:39 -07:00 |
|
Alex Forencich
|
cf3029364d
|
Add P-Tile example design core module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:13 -07:00 |
|
Alex Forencich
|
2a727e04f7
|
Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:53:34 -07:00 |
|
Alex Forencich
|
3f334dbbbb
|
Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:32:51 -07:00 |
|
Alex Forencich
|
e2588cd995
|
Clean up TCL scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 16:23:54 -07:00 |
|
Alex Forencich
|
743f3817ce
|
Fix alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-11 23:36:53 -07:00 |
|
Alex Forencich
|
e15fe3cbc9
|
Fix port widths
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-11 23:32:19 -07:00 |
|
Alex Forencich
|
edd1d546d5
|
Fix 256-bit RC interface framing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-06 23:14:19 -07:00 |
|
Alex Forencich
|
ce233c6c2b
|
Use latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 13:17:55 -07:00 |
|
Alex Forencich
|
a17c33e3c6
|
Update example designs to enable TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 01:31:15 -07:00 |
|
Alex Forencich
|
19b1af0388
|
Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-04 00:46:07 -07:00 |
|
Alex Forencich
|
103d7abdd9
|
Rework framing signal generation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-03 22:38:16 -07:00 |
|
Alex Forencich
|
a44f9852c2
|
Update Stratix 10 H-tile/L-tile shim to support segments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:48:46 -07:00 |
|
Alex Forencich
|
26c7128b7e
|
Tie off unused port
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:42:03 -07:00 |
|
Alex Forencich
|
24dd0af398
|
Adjust MSI-X TLP port configuration for single segment, single DWORD operations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-02 23:41:51 -07:00 |
|