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226 Commits

Author SHA1 Message Date
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
d6fc68947b Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 20:25:08 -07:00
Alex Forencich
78284572ef Remove XDC constraints that do not apply to Artix 7 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 18:35:22 -07:00
Alex Forencich
b1177eb4ed Rename HXT100G to HTG-640 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:26 -07:00
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
f4a8561652 Add HTG-9200 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:59 -07:00
Alex Forencich
6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:20 -07:00
Alex Forencich
31901754a6 Add FMC pins to VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:55 -07:00
Alex Forencich
19a76cbaf9 Add FMC pins to VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:44 -07:00
Alex Forencich
72a35c08ef Clean up FMC+ pins on HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:19 -07:00
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
375b12865f Use QSFP Si570 for both QSFP modules on VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:00:33 -07:00
Alex Forencich
1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 11:05:24 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00
Alex Forencich
412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:34:53 -07:00
Alex Forencich
026a302c1c Use unified 10G/25G design for ExaNIC X25 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:45:47 -07:00
Alex Forencich
5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:42:40 -07:00
Alex Forencich
a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:40:38 -07:00
Alex Forencich
147435dfe1 Use unified 10G/25G design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:38:34 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00
Alex Forencich
0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:49:25 -07:00
Alex Forencich
489ee73355 Use unified 10G/25G design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:02:57 -07:00
Alex Forencich
729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:59:33 -07:00
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
b6a9092a9f Update makefiles for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:46:34 -07:00
Alex Forencich
c4376c8674 Update XDC files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:12:32 -07:00
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 15:07:45 -08:00
Alex Forencich
7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 14:57:46 -08:00
Alex Forencich
f3d5e74527 Add RV901T example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 22:03:14 -08:00
Alex Forencich
8c3df76b97 Fix signal name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-27 18:26:58 -08:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
8e60adf567 Update axis_switch instances 2021-11-29 14:43:01 -08:00
Alex Forencich
d052264659 Add 520N-MX 10G example design 2021-11-03 00:48:06 -07:00
Alex Forencich
9e44987f60 Reorganize PHY instances 2021-11-02 23:30:48 -07:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
9ff4454db0 Update makefiles 2021-10-20 17:21:58 -07:00