Alex Forencich
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75c2cc0acc
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Use quad wrappers in HTG9200 example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-25 01:24:26 -07:00 |
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Alex Forencich
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aaeeb05ac0
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Fix PHY configuration connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-25 00:09:38 -07:00 |
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Alex Forencich
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fa05d4ff3c
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Add TX and RX enable inputs to MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-24 01:24:33 -07:00 |
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Alex Forencich
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20c542051d
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Use cfg prefix for configuration signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-22 17:14:52 -07:00 |
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Alex Forencich
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d6fc68947b
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Procedural generation of testbench drivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-27 20:25:08 -07:00 |
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Alex Forencich
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5d349c9cb2
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Enable overtemp shutdown in constraints files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-21 18:17:12 -07:00 |
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Alex Forencich
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f4a8561652
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Add HTG-9200 + HTG 6x QSFP28 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-21 18:16:59 -07:00 |
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Alex Forencich
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72a35c08ef
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Clean up FMC+ pins on HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-21 16:55:19 -07:00 |
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Alex Forencich
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bdc974a60c
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Reorganize HTG-9200 PLL config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-21 16:34:11 -07:00 |
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Alex Forencich
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efb3747967
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Add IO delay false paths to HTG-9200 constraints file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-20 21:15:20 -07:00 |
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Alex Forencich
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4a65e3594c
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Connect all PLL control lines on HTG-9200 board
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-20 01:17:49 -07:00 |
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Alex Forencich
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50b6f53387
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Update testbench clock frequencies
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-15 01:53:31 -07:00 |
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Alex Forencich
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d3fb11b2c3
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Use unified 10G/25G design for HTG9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 21:35:42 -07:00 |
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Alex Forencich
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48cbe43fa7
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Update Vivado makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 18:48:34 -07:00 |
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Alex Forencich
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c65161e696
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Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-17 16:04:16 -08:00 |
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Alex Forencich
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57803eeeb8
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Remove deprecated assignments
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-24 15:07:45 -08:00 |
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Alex Forencich
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7a0e88ffea
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Update vivado.mk
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-13 14:57:46 -08:00 |
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Alex Forencich
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1f80696b55
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Use start_soon instead of fork
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2021-12-10 18:19:11 -08:00 |
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Alex Forencich
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74f32c6a59
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Add missing PHY instance ports
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2021-11-02 20:28:26 -07:00 |
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Alex Forencich
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6b18e56cb1
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Add default_nettype none and resetall directives
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2021-10-20 17:29:12 -07:00 |
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Alex Forencich
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0f2478d68c
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Fix wires
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2021-10-20 17:21:16 -07:00 |
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Alex Forencich
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9f6f388a3c
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Rework GT instances in HTG9200 design
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2021-10-20 00:57:11 -07:00 |
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Alex Forencich
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4aa672f8f3
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Update example designs
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2021-10-17 20:20:26 -07:00 |
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Alex Forencich
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29313d5e02
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Add HTG-9200 10G example design
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2021-07-08 11:58:04 -07:00 |
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