16 Commits

Author	SHA1	Message	Date
Alex Forencich	bdc974a60c	Reorganize HTG-9200 PLL config ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-21 16:34:11 -07:00
Alex Forencich	efb3747967	Add IO delay false paths to HTG-9200 constraints file ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-20 21:15:20 -07:00
Alex Forencich	4a65e3594c	Connect all PLL control lines on HTG-9200 board ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-20 01:17:49 -07:00
Alex Forencich	50b6f53387	Update testbench clock frequencies ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-15 01:53:31 -07:00
Alex Forencich	d3fb11b2c3	Use unified 10G/25G design for HTG9200 ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-13 21:35:42 -07:00
Alex Forencich	48cbe43fa7	Update Vivado makefiles ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-07-13 18:48:34 -07:00
Alex Forencich	c65161e696	Remove recursively-expanded macros for module parameters in makefiles ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-02-17 16:04:16 -08:00
Alex Forencich	57803eeeb8	Remove deprecated assignments ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-01-24 15:07:45 -08:00
Alex Forencich	7a0e88ffea	Update vivado.mk ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2023-01-13 14:57:46 -08:00
Alex Forencich	1f80696b55	Use start_soon instead of fork	2021-12-10 18:19:11 -08:00
Alex Forencich	74f32c6a59	Add missing PHY instance ports	2021-11-02 20:28:26 -07:00
Alex Forencich	6b18e56cb1	Add default_nettype none and resetall directives	2021-10-20 17:29:12 -07:00
Alex Forencich	0f2478d68c	Fix wires	2021-10-20 17:21:16 -07:00
Alex Forencich	9f6f388a3c	Rework GT instances in HTG9200 design	2021-10-20 00:57:11 -07:00
Alex Forencich	4aa672f8f3	Update example designs	2021-10-17 20:20:26 -07:00
Alex Forencich	29313d5e02	Add HTG-9200 10G example design	2021-07-08 11:58:04 -07:00