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13 Commits

Author SHA1 Message Date
Alex Forencich
8d9da455cd Minor optimizations 2018-10-25 10:29:31 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
d50c767482 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter 2017-11-20 20:12:43 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
4f66059d21 Adjust constant naming 2016-06-27 11:27:04 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
9cca78bc7c Fix last cycle detect logic 2015-04-19 23:33:34 -07:00
Alex Forencich
7795a9182b Remove tristate for state machine inference 2015-04-19 23:08:41 -07:00
Alex Forencich
f827b5eafb Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00